[Meego-kernel] [MFLD Camera - PATCH v5 3/8] Medfield Camera Image ISP driver for V4L2 framework.
Wang, Wen W
wen.w.wang at intel.com
Fri Dec 17 02:56:01 PST 2010
>From ed74130f1d410536a60252437ebdb51745bff49f Mon Sep 17 00:00:00 2001
From: Wen Wang <wen.w.wang at intel.com>
Date: Sat, 18 Dec 2010 00:17:39 +0800
Subject: [PATCH] Medfield Camera Image ISP driver for V4L2 framework
This patch include Medfield camera image ISP driver V4L2 interface code.
It also includes header files for V4L2 related defines.
Signed-off-by: Wen Wang <wen.w.wang at intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
---
.../media/video/atomisp/include/mfldisp/ispparam.h | 354 ++
.../media/video/atomisp/include/mfldisp/mfld_mem.h | 82 +
.../atomisp/include/mfldisp/mfldisp_internal.h | 134 +
.../video/atomisp/include/mfldisp/mfldisp_sensor.h | 67 +
.../video/atomisp/include/mfldisp/mfldisp_v4l2.h | 211 +
.../media/video/atomisp/include/mfldisp/sp.map.h | 2346 +++++++++++
.../video/atomisp/include/mfldisp/to_upstream.h | 44 +
drivers/media/video/atomisp/mfldisp_v4l2.c | 4303 ++++++++++++++++++++
8 files changed, 7541 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/video/atomisp/include/mfldisp/ispparam.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/mfld_mem.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/mfldisp_internal.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/mfldisp_sensor.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/mfldisp_v4l2.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/sp.map.h
create mode 100644 drivers/media/video/atomisp/include/mfldisp/to_upstream.h
create mode 100644 drivers/media/video/atomisp/mfldisp_v4l2.c
diff --git a/drivers/media/video/atomisp/include/mfldisp/ispparam.h b/drivers/media/video/atomisp/include/mfldisp/ispparam.h
new file mode 100644
index 0000000..fb077e6
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/ispparam.h
@@ -0,0 +1,354 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+/*
+ * structure for handling ISP parameters,
+ *
+ * this structure will shared both in kernel/user space
+ */
+#ifndef ISP_PARAM_H_
+#define ISP_PARAM_H_
+
+unsigned short default_gamma_table[sh_css_gamma_table_size] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16,
+ 17, 18, 19, 20, 21, 23, 24, 25, 27, 28, 29, 31, 32, 33, 35, 36,
+ 38, 39, 41, 42, 44, 45, 47, 48, 49, 51, 52, 54, 55, 57, 58, 60,
+ 61, 62, 64, 65, 66, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 93, 94,
+ 95, 96, 97, 98, 98, 99, 100, 101, 102, 102, 103, 104, 105, 105, 106,
+ 107,
+ 108, 108, 109, 110, 110, 111, 112, 112, 113, 114, 114, 115, 116, 116,
+ 117, 118,
+ 118, 119, 120, 120, 121, 121, 122, 123, 123, 124, 125, 125, 126, 126,
+ 127, 127, /* 128 */
+ 128, 129, 129, 130, 130, 131, 131, 132, 132, 133, 134, 134, 135, 135,
+ 136, 136,
+ 137, 137, 138, 138, 139, 139, 140, 140, 141, 141, 142, 142, 143, 143,
+ 144, 144,
+ 145, 145, 145, 146, 146, 147, 147, 148, 148, 149, 149, 150, 150, 150,
+ 151, 151,
+ 152, 152, 152, 153, 153, 154, 154, 155, 155, 155, 156, 156, 156, 157,
+ 157, 158,
+ 158, 158, 159, 159, 160, 160, 160, 161, 161, 161, 162, 162, 162, 163,
+ 163, 163,
+ 164, 164, 164, 165, 165, 165, 166, 166, 166, 167, 167, 167, 168, 168,
+ 168, 169,
+ 169, 169, 170, 170, 170, 170, 171, 171, 171, 172, 172, 172, 172, 173,
+ 173, 173,
+ 174, 174, 174, 174, 175, 175, 175, 176, 176, 176, 176, 177, 177, 177,
+ 177, 178, /* 256 */
+ 178, 178, 178, 179, 179, 179, 179, 180, 180, 180, 180, 181, 181, 181,
+ 181, 182,
+ 182, 182, 182, 182, 183, 183, 183, 183, 184, 184, 184, 184, 184, 185,
+ 185, 185,
+ 185, 186, 186, 186, 186, 186, 187, 187, 187, 187, 187, 188, 188, 188,
+ 188, 188,
+ 189, 189, 189, 189, 189, 190, 190, 190, 190, 190, 191, 191, 191, 191,
+ 191, 192,
+ 192, 192, 192, 192, 192, 193, 193, 193, 193, 193, 194, 194, 194, 194,
+ 194, 194,
+ 195, 195, 195, 195, 195, 195, 196, 196, 196, 196, 196, 196, 197, 197,
+ 197, 197,
+ 197, 197, 198, 198, 198, 198, 198, 198, 198, 199, 199, 199, 199, 199,
+ 199, 200,
+ 200, 200, 200, 200, 200, 200, 201, 201, 201, 201, 201, 201, 201, 202,
+ 202, 202, /* 384 */
+ 202, 202, 202, 202, 203, 203, 203, 203, 203, 203, 203, 204, 204, 204,
+ 204, 204,
+ 204, 204, 204, 205, 205, 205, 205, 205, 205, 205, 205, 206, 206, 206,
+ 206, 206,
+ 206, 206, 206, 207, 207, 207, 207, 207, 207, 207, 207, 208, 208, 208,
+ 208, 208,
+ 208, 208, 208, 209, 209, 209, 209, 209, 209, 209, 209, 209, 210, 210,
+ 210, 210,
+ 210, 210, 210, 210, 210, 211, 211, 211, 211, 211, 211, 211, 211, 211,
+ 212, 212,
+ 212, 212, 212, 212, 212, 212, 212, 213, 213, 213, 213, 213, 213, 213,
+ 213, 213,
+ 214, 214, 214, 214, 214, 214, 214, 214, 214, 214, 215, 215, 215, 215,
+ 215, 215,
+ 215, 215, 215, 216, 216, 216, 216, 216, 216, 216, 216, 216, 216, 217,
+ 217, 217, /* 512 */
+ 217, 217, 217, 217, 217, 217, 217, 218, 218, 218, 218, 218, 218, 218,
+ 218, 218,
+ 218, 219, 219, 219, 219, 219, 219, 219, 219, 219, 219, 220, 220, 220,
+ 220, 220,
+ 220, 220, 220, 220, 220, 221, 221, 221, 221, 221, 221, 221, 221, 221,
+ 221, 221,
+ 222, 222, 222, 222, 222, 222, 222, 222, 222, 222, 223, 223, 223, 223,
+ 223, 223,
+ 223, 223, 223, 223, 223, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224,
+ 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 226, 226, 226,
+ 226, 226,
+ 226, 226, 226, 226, 226, 226, 226, 227, 227, 227, 227, 227, 227, 227,
+ 227, 227,
+ 227, 227, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228,
+ 229, 229,
+ 229, 229, 229, 229, 229, 229, 229, 229, 229, 229, 230, 230, 230, 230,
+ 230, 230,
+ 230, 230, 230, 230, 230, 230, 231, 231, 231, 231, 231, 231, 231, 231,
+ 231, 231,
+ 231, 231, 231, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232,
+ 232, 233,
+ 233, 233, 233, 233, 233, 233, 233, 233, 233, 233, 233, 233, 234, 234,
+ 234, 234,
+ 234, 234, 234, 234, 234, 234, 234, 234, 234, 235, 235, 235, 235, 235,
+ 235, 235,
+ 235, 235, 235, 235, 235, 235, 236, 236, 236, 236, 236, 236, 236, 236,
+ 236, 236,
+ 236, 236, 236, 236, 237, 237, 237, 237, 237, 237, 237, 237, 237, 237,
+ 237, 237,
+ 237, 237, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238,
+ 238, 238,
+ 239, 239, 239, 239, 239, 239, 239, 239, 239, 239, 239, 239, 239, 239,
+ 240, 240,
+ 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 241, 241,
+ 241, 241,
+ 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 242, 242, 242,
+ 242, 242,
+ 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 243, 243, 243, 243,
+ 243, 243,
+ 243, 243, 243, 243, 243, 243, 243, 243, 243, 244, 244, 244, 244, 244,
+ 244, 244,
+ 244, 244, 244, 244, 244, 244, 244, 244, 245, 245, 245, 245, 245, 245,
+ 245, 245,
+ 245, 245, 245, 245, 245, 245, 245, 246, 246, 246, 246, 246, 246, 246,
+ 246, 246,
+ 246, 246, 246, 246, 246, 246, 246, 247, 247, 247, 247, 247, 247, 247,
+ 247, 247,
+ 247, 247, 247, 247, 247, 247, 247, 248, 248, 248, 248, 248, 248, 248,
+ 248, 248,
+ 248, 248, 248, 248, 248, 248, 248, 249, 249, 249, 249, 249, 249, 249,
+ 249, 249,
+ 249, 249, 249, 249, 249, 249, 249, 250, 250, 250, 250, 250, 250, 250,
+ 250, 250,
+ 250, 250, 250, 250, 250, 250, 250, 251, 251, 251, 251, 251, 251, 251,
+ 251, 251,
+ 251, 251, 251, 251, 251, 251, 251, 252, 252, 252, 252, 252, 252, 252,
+ 252, 252,
+ 252, 252, 252, 252, 252, 252, 252, 253, 253, 253, 253, 253, 253, 253,
+ 253, 253,
+ 253, 253, 253, 253, 253, 253, 253, 253, 254, 254, 254, 254, 254, 254,
+ 254, 254,
+ 254, 254, 254, 254, 254, 254, 254, 254, 255, 255, 255, 255, 255, 255,
+ 255, 255
+};
+
+unsigned short default_ctc_table[sh_css_ctc_table_size] = {
+ 0, 0, 256, 384, 384, 497, 765, 806, 837, 851, 888, 901, 957, 981, 993,
+ 1001,
+ 1011, 1029, 1028, 1039, 1062, 1059, 1073, 1080, 1083, 1085, 1085, 1098,
+ 1080, 1084, 1085, 1093,
+ 1078, 1073, 1070, 1069, 1077, 1066, 1072, 1063, 1053, 1044, 1046, 1053,
+ 1039, 1028, 1025, 1024,
+ 1012, 1013, 1016, 996, 992, 990, 990, 980, 969, 968, 961, 955, 951, 949,
+ 933, 930,
+ 929, 925, 921, 916, 906, 901, 895, 893, 886, 877, 872, 869, 866, 861,
+ 857, 849,
+ 845, 838, 836, 832, 823, 821, 815, 813, 809, 805, 796, 793, 790, 785,
+ 784, 778,
+ 772, 768, 766, 763, 758, 752, 749, 745, 741, 740, 736, 730, 726, 724,
+ 723, 718,
+ 711, 709, 706, 704, 701, 698, 691, 689, 688, 683, 683, 678, 675, 673,
+ 671, 669,
+ 666, 663, 661, 660, 656, 656, 653, 650, 648, 647, 646, 643, 639, 638,
+ 637, 635,
+ 633, 632, 629, 627, 626, 625, 622, 621, 618, 618, 614, 614, 612, 609,
+ 606, 606,
+ 603, 600, 600, 597, 594, 591, 590, 586, 582, 581, 578, 575, 572, 569,
+ 563, 560,
+ 557, 554, 551, 548, 545, 539, 536, 533, 529, 527, 524, 519, 516, 513,
+ 510, 507,
+ 504, 501, 498, 493, 491, 488, 485, 484, 480, 476, 474, 471, 467, 466,
+ 464, 460,
+ 459, 455, 453, 449, 447, 446, 443, 441, 438, 435, 432, 432, 429, 427,
+ 426, 422,
+ 419, 418, 416, 414, 412, 410, 408, 406, 404, 402, 401, 398, 397, 395,
+ 393, 390,
+ 389, 388, 387, 384, 382, 380, 378, 377, 376, 375, 372, 370, 368, 368,
+ 366, 364,
+ 363, 361, 360, 358, 357, 355, 354, 352, 351, 350, 349, 346, 345, 344,
+ 344, 342,
+ 340, 339, 337, 337, 336, 335, 333, 331, 330, 329, 328, 326, 326, 324,
+ 324, 322,
+ 321, 320, 318, 318, 318, 317, 315, 313, 312, 311, 311, 310, 308, 307,
+ 306, 306,
+ 304, 304, 302, 301, 300, 300, 299, 297, 297, 296, 296, 294, 294, 292,
+ 291, 291,
+ 291, 290, 288, 287, 286, 286, 287, 285, 284, 283, 282, 282, 281, 281,
+ 279, 278,
+ 278, 278, 276, 276, 275, 274, 274, 273, 271, 270, 269, 268, 268, 267,
+ 265, 262,
+ 261, 260, 260, 259, 257, 254, 252, 252, 251, 251, 249, 246, 245, 244,
+ 243, 242,
+ 240, 239, 239, 237, 235, 235, 233, 231, 232, 230, 229, 226, 225, 224,
+ 225, 224,
+ 223, 220, 219, 219, 218, 217, 217, 214, 213, 213, 212, 211, 209, 209,
+ 209, 208,
+ 206, 205, 204, 203, 204, 203, 201, 200, 199, 197, 198, 198, 197, 195,
+ 194, 194,
+ 193, 192, 192, 191, 189, 190, 189, 188, 186, 187, 186, 185, 185, 184,
+ 183, 181,
+ 183, 182, 181, 180, 179, 178, 178, 178, 177, 176, 175, 176, 175, 174,
+ 174, 173,
+ 172, 173, 172, 171, 170, 170, 169, 169, 169, 168, 167, 166, 167, 167,
+ 166, 165,
+ 164, 164, 164, 163, 164, 163, 162, 163, 162, 161, 160, 161, 160, 160,
+ 160, 159,
+ 158, 157, 158, 158, 157, 157, 156, 156, 156, 156, 155, 155, 154, 154,
+ 154, 154,
+ 154, 153, 152, 153, 152, 152, 151, 152, 151, 152, 151, 150, 150, 149,
+ 149, 150,
+ 149, 149, 148, 148, 148, 149, 148, 147, 146, 146, 147, 146, 147, 146,
+ 145, 146,
+ 146, 145, 144, 145, 144, 145, 144, 144, 143, 143, 143, 144, 143, 142,
+ 142, 142,
+ 142, 142, 142, 141, 141, 141, 141, 140, 140, 141, 140, 140, 141, 140,
+ 139, 139,
+ 139, 140, 139, 139, 138, 138, 137, 139, 138, 138, 138, 137, 138, 137,
+ 137, 137,
+ 137, 136, 137, 136, 136, 136, 136, 135, 136, 135, 135, 135, 135, 136,
+ 135, 135,
+ 134, 134, 133, 135, 134, 134, 134, 133, 134, 133, 134, 133, 133, 132,
+ 133, 133,
+ 132, 133, 132, 132, 132, 132, 131, 131, 131, 132, 131, 131, 130, 131,
+ 130, 132,
+ 131, 130, 130, 129, 130, 129, 130, 129, 129, 129, 130, 129, 128, 128,
+ 128, 128,
+ 129, 128, 128, 127, 127, 128, 128, 127, 127, 126, 126, 127, 127, 126,
+ 126, 126,
+ 127, 126, 126, 126, 125, 125, 126, 125, 125, 124, 124, 124, 125, 125,
+ 124, 124,
+ 123, 124, 124, 123, 123, 122, 122, 122, 122, 122, 121, 120, 120, 119,
+ 118, 118,
+ 118, 117, 117, 116, 115, 115, 115, 114, 114, 113, 113, 112, 111, 111,
+ 111, 110,
+ 110, 109, 109, 108, 108, 108, 107, 107, 106, 106, 105, 105, 105, 104,
+ 104, 103,
+ 103, 102, 102, 102, 102, 101, 101, 100, 100, 99, 99, 99, 99, 99, 99, 98,
+ 97, 98, 97, 97, 97, 96, 96, 95, 96, 95, 96, 95, 95, 94, 94, 95,
+ 94, 94, 94, 93, 93, 92, 93, 93, 93, 93, 92, 92, 91, 92, 92, 92,
+ 91, 91, 90, 90, 91, 91, 91, 90, 90, 90, 90, 91, 90, 90, 90, 89,
+ 89, 89, 90, 89, 89, 89, 89, 89, 88, 89, 89, 88, 88, 88, 88, 87,
+ 89, 88, 88, 88, 88, 88, 87, 88, 88, 88, 87, 87, 87, 87, 87, 88,
+ 87, 87, 87, 87, 87, 87, 88, 87, 87, 87, 87, 86, 86, 87, 87, 87,
+ 87, 86, 86, 86, 87, 87, 86, 87, 86, 86, 86, 87, 87, 86, 86, 86,
+ 86, 86, 87, 87, 86, 85, 85, 85, 84, 85, 85, 84, 84, 83, 83, 82,
+ 82, 82, 81, 81, 80, 79, 79, 79, 78, 77, 77, 76, 76, 76, 75, 74,
+ 74, 74, 73, 73, 72, 71, 71, 71, 70, 70, 69, 69, 68, 68, 67, 67,
+ 67, 66, 66, 65, 65, 64, 64, 63, 62, 62, 62, 61, 60, 60, 59, 59,
+ 58, 58, 57, 57, 56, 56, 56, 55, 55, 54, 55, 55, 54, 53, 53, 52,
+ 53, 53, 52, 51, 51, 50, 51, 50, 49, 49, 50, 49, 49, 48, 48, 47,
+ 47, 48, 46, 45, 45, 45, 46, 45, 45, 44, 45, 45, 45, 43, 42, 42,
+ 41, 43, 41, 40, 40, 39, 40, 41, 39, 39, 39, 39, 39, 38, 35, 35,
+ 34, 37, 36, 34, 33, 33, 33, 35, 34, 32, 32, 31, 32, 30, 29, 26,
+ 25, 25, 27, 26, 23, 23, 23, 25, 24, 24, 22, 21, 20, 19, 16, 14,
+ 13, 13, 13, 10, 9, 7, 7, 7, 12, 12, 12, 7, 0, 0, 0, 0
+};
+
+/* multiple axis color correction table, 64values = 2x2matrix
+ * for 16area, 1value per 16bit */
+const short default_macc_table[sh_css_num_macc_axes * 4] = {
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256
+};
+
+const short blue_macc_table[sh_css_num_macc_axes * 4] = {
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256
+};
+
+const short green_macc_table[sh_css_num_macc_axes * 4] = {
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256
+};
+
+const short skin_macc_table[sh_css_num_macc_axes * 4] = {
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256,
+ 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256, 256, 0, 0, 256
+};
+
+struct sh_css_isp_cc_config default_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, -374, -342, 0, -672, 301},
+};
+
+struct hCss_isp_cc_config sepia_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, -374, -342, 0, -672, 301},
+};
+
+struct sh_css_isp_cc_config negative_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, -374, -342, 0, -672, 301},
+};
+
+struct sh_css_isp_cc_config mono_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, -374, -342, 0, -672, 301},
+};
+
+struct sh_css_isp_tnr_config default_tnr_config = {
+ .gain = 32768,
+ .threshold_y = 32,
+ .threshold_uv = 32,
+};
+
+struct sh_css_isp_ob_config default_ob_config = {
+ .mode = sh_css_isp_ob_mode_none,
+ .level_gr = 0,
+ .level_r = 0,
+ .level_b = 0,
+ .level_gb = 0,
+ .start_position = 0,
+ .end_position = 0
+};
+
+struct sh_css_isp_nr_config default_nr_config = {
+ .gain = 16384,
+ .direction = 1280,
+ .threshold_cb = 0,
+ .threshold_cr = 0
+};
+
+struct sh_css_isp_ee_config default_ee_config = {
+ .gain = 8192,
+ .threshold = 128,
+ .detail_gain = 2048
+};
+
+struct sh_css_isp_dp_config default_dp_config = {
+ .threshold = 8192,
+ .gain = 2048
+};
+
+#endif /* ISP_PARAM_H_ */
diff --git a/drivers/media/video/atomisp/include/mfldisp/mfld_mem.h b/drivers/media/video/atomisp/include/mfldisp/mfld_mem.h
new file mode 100644
index 0000000..0bf773e
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/mfld_mem.h
@@ -0,0 +1,82 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifndef _MFLD_MEM_H
+#define _MFLD_MEM_H
+
+#include "mfldisp_v4l2.h"
+
+#define mfld_write_bits_8(a, d) (*(char *)get_io_virt_addr(a) = d)
+#define mfld_write_bits_16(a, d) (*(short *)get_io_virt_addr(a) = d)
+#define mfld_write_bits_32(a, d) (*(int *)get_io_virt_addr(a) = d)
+
+#define mfld_write_bits_8_volatile(a, d) (*(char *)get_io_virt_addr(a) = d)
+#define mfld_write_bits_16_volatile(a, d) (*(short *)get_io_virt_addr(a) = d)
+#define mfld_write_bits_32_volatile(a, d) (*(int *)get_io_virt_addr(a) = d)
+
+#define mfld_read_bits_8(a) (*(char *)get_io_virt_addr(a))
+#define mfld_read_bits_16(a) (*(short *)get_io_virt_addr(a))
+#define mfld_read_bits_32(a) (*(int *)get_io_virt_addr(a))
+
+#define mfld_read_bits_8_volatile(a) (*(char *)get_io_virt_addr(a))
+#define mfld_read_bits_16_volatile(a) (*(short *)get_io_virt_addr(a))
+#define mfld_read_bits_32_volatile(a) (*(int *)get_io_virt_addr(a))
+
+#define mfld_read_bits_u8(a) (*(unsigned char *)get_io_virt_addr(a))
+#define mfld_read_bits_u16(a) (*(unsigned short *)get_io_virt_addr(a))
+#define mfld_read_bits_u32(a) (*(unsigned int *)get_io_virt_addr(a))
+
+#define mfld_read_bits_u8_volatile(a) (*(unsigned char *)get_io_virt_addr(a))
+#define mfld_read_bits_u16_volatile(a) (*(unsigned short *)get_io_virt_addr(a))
+#define mfld_read_bits_u32_volatile(a) (*(unsigned int *)get_io_virt_addr(a))
+
+static inline void *_hrt_mem_store(void *to, const void *from, size_t n)
+{
+ unsigned i;
+ unsigned int _to = (unsigned int)to;
+ const char *_from = (const char *)from;
+ for (i = 0; i < n; i++, _to++, _from++)
+ mfld_write_bits_8(_to, *_from);
+ return (void *)_to;
+}
+
+static inline void *_hrt_mem_load(const void *from, void *to, size_t n)
+{
+ unsigned i;
+ char *_to = (char *)to;
+ unsigned int _from = (unsigned int)from;
+ for (i = 0; i < n; i++, _to++, _from++)
+ *_to = mfld_read_bits_8(_from);
+ return _to;
+}
+
+static inline void *_hrt_mem_set(void *to, int c, size_t n)
+{
+ unsigned i;
+ unsigned int _to = (unsigned int)to;
+ for (i = 0; i < n; i++, _to++)
+ mfld_write_bits_8(_to, c);
+ return (void *)_to;
+}
+
+#endif /* _MFLD_MEM_H */
diff --git a/drivers/media/video/atomisp/include/mfldisp/mfldisp_internal.h b/drivers/media/video/atomisp/include/mfldisp/mfldisp_internal.h
new file mode 100644
index 0000000..cc389bf
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/mfldisp_internal.h
@@ -0,0 +1,134 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef MFLDISP_INTERNAL_H_
+#define MFLDISP_INTERNAL_H_
+
+#include <linux/kernel.h>
+
+#define LOG_LENGTH 100
+#define ISP_NAME "atomisp"
+#define mfld_isp_dbg(level, fmt, arg...) do {\
+ if (!(strcmp(level, KERN_INFO)) || \
+ !(strcmp(level, KERN_ERR))) {\
+ printk(level "%s: " fmt, "atomisp", ##arg); \
+ } \
+} while (0)
+
+extern void hrt_isp_css_mm_set_user_ptr(unsigned int userptr,
+ unsigned int num_pages);
+#ifdef USE_DYNAMIC_BIN
+#define HIVE_ADDR_sp_dma_proxy_run_entry 0x767
+#define HIVE_ADDR_sp_dma_proxy_init_entry 0xC42
+#define HIVE_ADDR_super_impose_offline_entry 0x543
+#define HIVE_ADDR_sp_gen_histogram_entry 0x420
+#define HIVE_ADDR_copy_frame_entry 0x2CD
+#define HIVE_ADDR_sp_bin_copy_entry 0x250
+#define HIVE_ADDR_sp_start_isp_entry 0x0
+
+#define _hrt_transfer_embedded_sp(code_func, data_func, bss_func, \
+ view_table_func, args...) \
+{\
+code_func(0x0, 0x0, 0x1E5F0, ## args);\
+data_func(scalar_processor_dmem, 0x4, 0x1E5F0, 0x2A1, ## args);\
+bss_func(scalar_processor_dmem, 0x2A8, 0x3860, ## args);\
+}
+
+
+extern char *_hrt_blob_sp;
+extern char *_hrt_blob_isp_bayer_ds_var;
+extern char *_hrt_blob_isp_copy_var;
+extern char *_hrt_blob_isp_primary_16mp;
+extern char *_hrt_blob_isp_primary_14mp;
+extern char *_hrt_blob_isp_primary_var;
+extern char *_hrt_blob_isp_primary_ds;
+extern char *_hrt_blob_isp_primary_small;
+extern char *_hrt_blob_isp_preview_var;
+extern char *_hrt_blob_isp_preview_ds;
+extern char *_hrt_blob_isp_video_online;
+extern char *_hrt_blob_isp_video_online_nodz;
+extern char *_hrt_blob_isp_video_online_ds;
+extern char *_hrt_blob_isp_video_offline;
+extern char *_hrt_blob_isp_xnr_var;
+extern char *_hrt_blob_isp_pregdc_var;
+extern char *_hrt_blob_isp_gdc_var;
+extern char *_hrt_blob_isp_postgdc_var;
+extern char *_hrt_blob_isp_vf_pp;
+
+extern unsigned int _hrt_text_size_of_sp;
+extern unsigned int _hrt_size_of_sp;
+
+extern unsigned int _hrt_text_size_of_isp_bayer_ds_var;
+extern unsigned int _hrt_size_of_isp_bayer_ds_var;
+
+extern unsigned int _hrt_text_size_of_isp_copy_var;
+extern unsigned int _hrt_size_of_isp_copy_var;
+
+extern unsigned int _hrt_text_size_of_isp_gdc_var;
+extern unsigned int _hrt_size_of_isp_gdc_var;
+
+extern unsigned int _hrt_text_size_of_isp_postgdc_var;
+extern unsigned int _hrt_size_of_isp_postgdc_var;
+
+extern unsigned int _hrt_text_size_of_isp_pregdc_var;
+extern unsigned int _hrt_size_of_isp_pregdc_var;
+
+extern unsigned int _hrt_text_size_of_isp_preview_ds;
+extern unsigned int _hrt_size_of_isp_preview_ds;
+
+extern unsigned int _hrt_text_size_of_isp_preview_var;
+extern unsigned int _hrt_size_of_isp_preview_var;
+
+extern unsigned int _hrt_text_size_of_isp_primary_14mp;
+extern unsigned int _hrt_size_of_isp_primary_14mp;
+
+extern unsigned int _hrt_text_size_of_isp_primary_16mp;
+extern unsigned int _hrt_size_of_isp_primary_16mp;
+
+extern unsigned int _hrt_text_size_of_isp_primary_ds;
+extern unsigned int _hrt_size_of_isp_primary_ds;
+
+extern unsigned int _hrt_text_size_of_isp_primary_small;
+extern unsigned int _hrt_size_of_isp_primary_small;
+
+extern unsigned int _hrt_text_size_of_isp_primary_var;
+extern unsigned int _hrt_size_of_isp_primary_var;
+
+extern unsigned int _hrt_text_size_of_isp_vf_pp;
+extern unsigned int _hrt_size_of_isp_vf_pp;
+
+extern unsigned int _hrt_text_size_of_isp_video_offline;
+extern unsigned int _hrt_size_of_isp_video_offline;
+
+extern unsigned int _hrt_text_size_of_isp_video_online_ds;
+extern unsigned int _hrt_size_of_isp_video_online_ds;
+
+extern unsigned int _hrt_text_size_of_isp_video_online_nodz;
+extern unsigned int _hrt_size_of_isp_video_online_nodz;
+
+extern unsigned int _hrt_text_size_of_isp_video_online;
+extern unsigned int _hrt_size_of_isp_video_online;
+
+extern unsigned int _hrt_text_size_of_isp_xnr_var;
+extern unsigned int _hrt_size_of_isp_xnr_var;
+#endif
+#endif /* MFLDISP_INTERNAL_H_ */
diff --git a/drivers/media/video/atomisp/include/mfldisp/mfldisp_sensor.h b/drivers/media/video/atomisp/include/mfldisp/mfldisp_sensor.h
new file mode 100644
index 0000000..f45782a
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/mfldisp_sensor.h
@@ -0,0 +1,67 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifndef _SensorParams_h_
+#define _SensorParams_h_
+
+#define MIPI_PORT_LANE_1 0
+#define MIPI_PORT_LANE_4 1
+
+
+#define BAYER_ORDER_GRBG 0
+#define BAYER_ORDER_RGGB 1
+#define BAYER_ORDER_BGGR 2
+#define BAYER_ORDER_GBRG 3
+
+#define INPUT_FORMAT_YUV420_8_LEGACY 0
+#define INPUT_FORMAT_YUV420_8 1
+#define INPUT_FORMAT_YUV420_10 2
+#define INPUT_FORMAT_YUV422_8 3
+#define INPUT_FORMAT_YUV422_10 4
+#define INPUT_FORMAT_RGB_444 5
+#define INPUT_FORMAT_RGB_555 6
+#define INPUT_FORMAT_RGB_565 7
+#define INPUT_FORMAT_RGB_666 8
+#define INPUT_FORMAT_RGB_888 9
+#define INPUT_FORMAT_RAW_6 10
+#define INPUT_FORMAT_RAW_7 11
+#define INPUT_FORMAT_RAW_8 12
+#define INPUT_FORMAT_RAW_10 13
+#define INPUT_FORMAT_RAW_12 14
+#define INPUT_FORMAT_RAW_14 15
+#define INPUT_FORMAT_RAW_16 16
+#define INPUT_FORMAT_BINARY_8 17
+
+struct mfld_ci_mipi_camera {
+ u32 port;
+ u32 num_of_lane;
+ u32 input_format;
+ u32 raw_bayer_order;
+ struct sh_css_shading_table*
+ (*get_shading_table)(unsigned int frame_width,
+ unsigned int frame_height,
+ unsigned int table_width,
+ unsigned int table_height);
+};
+
+#endif /* _SensorParams_h_ */
diff --git a/drivers/media/video/atomisp/include/mfldisp/mfldisp_v4l2.h b/drivers/media/video/atomisp/include/mfldisp/mfldisp_v4l2.h
new file mode 100644
index 0000000..1616b64
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/mfldisp_v4l2.h
@@ -0,0 +1,211 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifndef MFLDISP_V4L2_H_
+#define MFLDISP_V4L2_H_
+
+#define ATOMISP_MAJOR 0
+#define ATOMISP_MINOR 3
+#define ATOMISP_PATCHLEVEL 1
+
+#define DRIVER_VERSION_STR __stringify(ATOMISP_MAJOR) \
+ "." __stringify(ATOMISP_MINOR) "." __stringify(ATOMISP_PATCHLEVEL)
+#define DRIVER_VERSION KERNEL_VERSION(ATOMISP_MAJOR, \
+ ATOMISP_MINOR, ATOMISP_PATCHLEVEL)
+
+#define CI_MODE_PREVIEW 0x8000
+#define CI_MODE_VIDEO 0x4000
+#define CI_MODE_STILL_CAPTURE 0x2000
+#define CI_MODE_NONE 0x0000
+
+void *get_io_virt_addr(unsigned int address);
+
+#define MFLD_CI_I2C_BUS_1 4
+#define MFLD_CI_I2C_BUS_2 5
+
+#define PRIMARY_CAMERA 0
+#define SECONDARY_CAMERA 1
+#define CAMERA_MOTOR 2
+#define XENON_FLASH 3
+#define LED_FLASH 4
+
+#define MFLD_ISP_STEP_WIDTH 2
+#define MFLD_ISP_STEP_HEIGHT 2
+
+#define MFLD_ISP_MAX_WIDTH 4608
+#define MFLD_ISP_MAX_HEIGHT 3450
+
+#define MFLD_ISP_MAX_WIDTH_TMP 1280
+#define MFLD_ISP_MAX_HEIGHT_TMP 720
+
+#include <linux/i2c.h>
+struct mfld_isp_subdev {
+ u32 subdev_type;
+ struct i2c_board_info board_info;
+ int i2c_adapter_id;
+};
+
+struct mfld_isp_3a_binary {
+ unsigned int mode;
+ int s3atbl_width;
+ int s3atbl_height;
+ int width;
+ int height;
+ int deci_factor;
+};
+
+#include "css/sh_css.h"
+
+struct mfld_isp_parm {
+ struct sh_css_grid_info info;
+ struct sh_css_isp_wb_config wb_config;
+ struct sh_css_isp_cc_config cc_config;
+ struct sh_css_isp_ob_config ob_config;
+ struct sh_css_isp_dp_config dp_config;
+ struct sh_css_isp_nr_config nr_config;
+ struct sh_css_isp_ee_config ee_config;
+ struct sh_css_isp_tnr_config tnr_config;
+};
+
+struct mfld_isp_dis_config {
+ int *w_sdis_vertproj_tbl;
+ int *w_sdis_horiproj_tbl;
+ short *sdis_vertcoef_tbl;
+ short *sdis_horicoef_tbl;
+ int dis_x;
+ int dis_y;
+};
+
+struct mfld_3a_stat {
+ void __user *w_3a_stat;
+};
+
+struct mfld_isp_gamma_tbl {
+ unsigned short gamma_table[1024];
+};
+
+/*Private IOCTLs for ISP */
+#define ATOMISP_IOC_G_XNR \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 0, int)
+#define ATOMISP_IOC_S_XNR \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 1, int)
+#define ATOMISP_IOC_G_BAYER_NR \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 2, struct sh_css_isp_nr_config)
+#define ATOMISP_IOC_S_BAYER_NR \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct sh_css_isp_nr_config)
+#define ATOMISP_IOC_G_TNR \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 4, struct sh_css_isp_tnr_config)
+#define ATOMISP_IOC_S_TNR \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 5, struct sh_css_isp_tnr_config)
+#define ATOMISP_IOC_G_HISTOGRAM \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 6, struct sh_css_histogram)
+#define ATOMISP_IOC_S_HISTOGRAM \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 7, struct sh_css_histogram)
+#define ATOMISP_IOC_G_BLACK_LEVEL_COMP \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 8, struct sh_css_isp_ob_config)
+#define ATOMISP_IOC_S_BLACK_LEVEL_COMP \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 9, struct sh_css_isp_ob_config)
+#define ATOMISP_IOC_G_YCC_NR \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct sh_css_isp_nr_config)
+#define ATOMISP_IOC_S_YCC_NR \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 11, struct sh_css_isp_nr_config)
+#define ATOMISP_IOC_G_EE \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 12, struct sh_css_isp_ee_config)
+#define ATOMISP_IOC_S_EE \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 13, struct sh_css_isp_ee_config)
+#define ATOMISP_IOC_G_DIS_STAT \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 14, struct mfld_isp_dis_config)
+#define ATOMISP_IOC_S_DIS_STAT \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 15, struct mfld_isp_dis_config)
+#define ATOMISP_IOC_G_3A_STAT \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 16, struct mfld_3a_stat)
+#define ATOMISP_IOC_G_ISP_PARM \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 17, struct mfld_isp_parm)
+#define ATOMISP_IOC_S_ISP_PARM \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 18, struct mfld_isp_parm)
+#define ATOMISP_IOC_G_ISP_GAMMA \
+ _IOR('v', BASE_VIDIOC_PRIVATE + 19, struct mfld_isp_gamma_tbl)
+#define ATOMISP_IOC_S_ISP_GAMMA \
+ _IOW('v', BASE_VIDIOC_PRIVATE + 20, struct mfld_isp_gamma_tbl)
+
+/*Extended IDs for Camera Class*/
+#include "to_upstream.h"
+
+/*Private control IDs*/
+#define V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION \
+ (V4L2_CID_PRIVATE_BASE + 0)
+#define V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC \
+ (V4L2_CID_PRIVATE_BASE + 1)
+#define V4L2_CID_ATOMISP_VIDEO_STABLIZATION \
+ (V4L2_CID_PRIVATE_BASE + 2)
+#define V4L2_CID_ATOMISP_FIXED_PATTERN_NR \
+ (V4L2_CID_PRIVATE_BASE + 3)
+#define V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION \
+ (V4L2_CID_PRIVATE_BASE + 4)
+#define V4L2_CID_ATOMISP_SHADING_CORRECTION \
+ (V4L2_CID_PRIVATE_BASE + 5)
+
+#ifdef USE_DYNAMIC_BIN
+/* This is for the firmware Loading from user space */
+struct bi_h {
+ int ID;
+ unsigned int offset;
+ unsigned int size;
+ unsigned int text_size;
+};
+
+struct bi_file_h {
+ int version;
+ int binary_nr;
+ unsigned int h_size;
+ unsigned int bi_offset;
+};
+
+enum isp_bin_binary_id {
+ isp_bin_sp,
+ isp_bin_copy_var,
+ isp_bin_bayer_ds_var,
+ isp_bin_vf_pp,
+ isp_bin_xnr_var,
+ isp_bin_pregdc_var,
+ isp_bin_gdc_var,
+ isp_bin_postgdc_var,
+ isp_bin_preview_var,
+ isp_bin_preview_ds,
+ isp_bin_primary_var,
+ isp_bin_primary_small,
+ isp_bin_primary_ds,
+ isp_bin_primary_14mp,
+ isp_bin_primary_16mp,
+ isp_bin_video_offline,
+ isp_bin_video_online,
+ isp_bin_video_online_nodz,
+ isp_bin_video_online_ds,
+ isp_binary_number,
+};
+
+#define FW_PATH "shisp.bin"
+#define SUPPORTED_BIN isp_binary_number
+#endif
+
+#endif /* MFLDISP_V4L2_H_ */
diff --git a/drivers/media/video/atomisp/include/mfldisp/sp.map.h b/drivers/media/video/atomisp/include/mfldisp/sp.map.h
new file mode 100644
index 0000000..273d5ae
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/sp.map.h
@@ -0,0 +1,2346 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _SP_MAP_H_
+#define _SP_MAP_H_
+
+#ifndef USE_DYNAMIC_BIN
+#include "./sp.blob.h"
+#endif
+
+#ifndef _hrt_dummy_use_blob_sp
+#define _hrt_dummy_use_blob_sp()
+#endif
+
+#define _hrt_cell_load_program_sp(proc) \
+ _hrt_cell_load_program_embedded(proc, sp)
+
+#if defined(HIVE_MEM_sp_uds_obuf_offset_u) && \
+ (HIVE_ADDR_sp_uds_obuf_offset_u != 0x357C || \
+ HIVE_SIZE_sp_uds_obuf_offset_u != 44)
+#error Symbol sp_uds_obuf_offset_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_obuf_offset_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_obuf_offset_u 0x357C
+#define HIVE_SIZE_sp_uds_obuf_offset_u 44
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_u) && \
+ (HIVE_ADDR_sp_si_bg_u != 0x35A8 || \
+ HIVE_SIZE_sp_si_bg_u != 4)
+#error Symbol sp_si_bg_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_u 0x35A8
+#define HIVE_SIZE_sp_si_bg_u 4
+#endif
+
+/* function sp_dma_proxy_read: D0B */
+#if defined(HIVE_MEM_sp_vf_crop_pos_x) && \
+ (HIVE_ADDR_sp_vf_crop_pos_x != 0x3178 || \
+ HIVE_SIZE_sp_vf_crop_pos_x != 4)
+#error Symbol sp_vf_crop_pos_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vf_crop_pos_x scalar_processor_dmem
+#define HIVE_ADDR_sp_vf_crop_pos_x 0x3178
+#define HIVE_SIZE_sp_vf_crop_pos_x 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_v_addr) && \
+ (HIVE_ADDR_sp_input_v_addr != 0x317C || \
+ HIVE_SIZE_sp_input_v_addr != 4)
+#error Symbol sp_input_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_v_addr 0x317C
+#define HIVE_SIZE_sp_input_v_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_icx_left_rounded_y) && \
+ (HIVE_ADDR_sp_uds_icx_left_rounded_y != 0x35AC || \
+ HIVE_SIZE_sp_uds_icx_left_rounded_y != 4)
+#error Symbol sp_uds_icx_left_rounded_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_icx_left_rounded_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_icx_left_rounded_y 0x35AC
+#define HIVE_SIZE_sp_uds_icx_left_rounded_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_horiproj_num) && \
+ (HIVE_ADDR_sp_sdis_horiproj_num != 0x3180 || \
+ HIVE_SIZE_sp_sdis_horiproj_num != 4)
+#error Symbol sp_sdis_horiproj_num occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_horiproj_num scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_horiproj_num 0x3180
+#define HIVE_SIZE_sp_sdis_horiproj_num 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_batr) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_batr != 0x35B0 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_batr != 4)
+#error Symbol sp_frame_ptr_qplane_batr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_batr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_batr 0x35B0
+#define HIVE_SIZE_sp_frame_ptr_qplane_batr 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_u) && \
+ (HIVE_ADDR_sp_si_blend_overlay_u != 0x35B4 || \
+ HIVE_SIZE_sp_si_blend_overlay_u != 4)
+#error Symbol sp_si_blend_overlay_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_u 0x35B4
+#define HIVE_SIZE_sp_si_blend_overlay_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_yuv420) && \
+ (HIVE_ADDR_sp_if_b_yuv420 != 0x35B8 || \
+ HIVE_SIZE_sp_if_b_yuv420 != 4)
+#error Symbol sp_if_b_yuv420 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_yuv420 scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_yuv420 0x35B8
+#define HIVE_SIZE_sp_if_b_yuv420 4
+#endif
+
+#if defined(HIVE_MEM_dma_proxy_status) && \
+ (HIVE_ADDR_dma_proxy_status != 0x4C || \
+ HIVE_SIZE_dma_proxy_status != 4)
+#error Symbol dma_proxy_status occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_dma_proxy_status scalar_processor_dmem
+#define HIVE_ADDR_dma_proxy_status 0x4C
+#define HIVE_SIZE_dma_proxy_status 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_gr) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_gr != 0x35BC || \
+ HIVE_SIZE_sp_frame_ptr_plane_gr != 4)
+#error Symbol sp_frame_ptr_plane_gr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_gr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_gr 0x35BC
+#define HIVE_SIZE_sp_frame_ptr_plane_gr 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_bytes_available) && \
+ (HIVE_ADDR_sp_bin_copy_bytes_available != 0x3184 || \
+ HIVE_SIZE_sp_bin_copy_bytes_available != 4)
+#error Symbol sp_bin_copy_bytes_available occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_bytes_available scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_bytes_available 0x3184
+#define HIVE_SIZE_sp_bin_copy_bytes_available 4
+#endif
+
+/* function sp_start_isp: 5 */
+#if defined(HIVE_MEM_sp_error) && \
+ (HIVE_ADDR_sp_error != 0x3534 || \
+ HIVE_SIZE_sp_error != 4)
+#error Symbol sp_error occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_error scalar_processor_dmem
+#define HIVE_ADDR_sp_error 0x3534
+#define HIVE_SIZE_sp_error 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_v) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_v != 0x35C0 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_v != 4)
+#error Symbol sp_frame_ptr_vfout_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_v 0x35C0
+#define HIVE_SIZE_sp_frame_ptr_vfout_v 4
+#endif
+
+/* function _initialize_sdis_coefficients: F1D */
+/* function _clear_vectors: EA8 */
+#if defined(HIVE_MEM_sp_frame_ptr_uv_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_prev != 0x35C4 || \
+ HIVE_SIZE_sp_frame_ptr_uv_prev != 4)
+#error Symbol sp_frame_ptr_uv_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_prev 0x35C4
+#define HIVE_SIZE_sp_frame_ptr_uv_prev 4
+#endif
+
+#if defined(HIVE_MEM_hres_in) && \
+ (HIVE_ADDR_hres_in != 0x3188 || \
+ HIVE_SIZE_hres_in != 4)
+#error Symbol hres_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_hres_in scalar_processor_dmem
+#define HIVE_ADDR_hres_in 0x3188
+#define HIVE_SIZE_hres_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_comp) && \
+ (HIVE_ADDR_sp_mipi_comp != 0x318C || \
+ HIVE_SIZE_sp_mipi_comp != 4)
+#error Symbol sp_mipi_comp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_comp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_comp 0x318C
+#define HIVE_SIZE_sp_mipi_comp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_v) && \
+ (HIVE_ADDR_sp_frame_ptr_v != 0x35C8 || \
+ HIVE_SIZE_sp_frame_ptr_v != 4)
+#error Symbol sp_frame_ptr_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v 0x35C8
+#define HIVE_SIZE_sp_frame_ptr_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_cropped_height) && \
+ (HIVE_ADDR_sp_if_a_cropped_height != 0x35CC || \
+ HIVE_SIZE_sp_if_a_cropped_height != 4)
+#error Symbol sp_if_a_cropped_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_cropped_height scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_cropped_height 0x35CC
+#define HIVE_SIZE_sp_if_a_cropped_height 4
+#endif
+
+/* function isp_pregdc_var_sp_main: 3373 */
+/* function hrt_isp_css_sp_store_isp_code: 3C65 */
+/* function sp_dma_proxy_init_entry: C42 */
+#ifdef HIVE_ADDR_sp_dma_proxy_init_entry
+#error Symbol sp_dma_proxy_init_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_dma_proxy_init_entry 0xC42
+#endif
+
+#if defined(HIVE_MEM_vf_log_scale) && \
+ (HIVE_ADDR_vf_log_scale != 0x3190 || \
+ HIVE_SIZE_vf_log_scale != 4)
+#error Symbol vf_log_scale occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vf_log_scale scalar_processor_dmem
+#define HIVE_ADDR_vf_log_scale 0x3190
+#define HIVE_SIZE_vf_log_scale 4
+#endif
+
+#if defined(HIVE_MEM_sp_enable_xnr) && \
+ (HIVE_ADDR_sp_enable_xnr != 0x35D0 || \
+ HIVE_SIZE_sp_enable_xnr != 4)
+#error Symbol sp_enable_xnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_enable_xnr scalar_processor_dmem
+#define HIVE_ADDR_sp_enable_xnr 0x35D0
+#define HIVE_SIZE_sp_enable_xnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_bayer1) && \
+ (HIVE_ADDR_sp_frame_ptr_bayer1 != 0x35D4 || \
+ HIVE_SIZE_sp_frame_ptr_bayer1 != 4)
+#error Symbol sp_frame_ptr_bayer1 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_bayer1 scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_bayer1 0x35D4
+#define HIVE_SIZE_sp_frame_ptr_bayer1 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_obuf_offset_y) && \
+ (HIVE_ADDR_sp_uds_obuf_offset_y != 0x35D8 || \
+ HIVE_SIZE_sp_uds_obuf_offset_y != 44)
+#error Symbol sp_uds_obuf_offset_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_obuf_offset_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_obuf_offset_y 0x35D8
+#define HIVE_SIZE_sp_uds_obuf_offset_y 44
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_u) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_u != 0x3604 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_u != 4)
+#error Symbol sp_frame_ptr_overlay_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_u 0x3604
+#define HIVE_SIZE_sp_frame_ptr_overlay_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_num_lanes) && \
+ (HIVE_ADDR_sp_mipi_num_lanes != 0x3194 || \
+ HIVE_SIZE_sp_mipi_num_lanes != 4)
+#error Symbol sp_mipi_num_lanes occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_num_lanes scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_num_lanes 0x3194
+#define HIVE_SIZE_sp_mipi_num_lanes 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_iy_topleft_u) && \
+ (HIVE_ADDR_sp_uds_iy_topleft_u != 0x3608 || \
+ HIVE_SIZE_sp_uds_iy_topleft_u != 4)
+#error Symbol sp_uds_iy_topleft_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_iy_topleft_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_iy_topleft_u 0x3608
+#define HIVE_SIZE_sp_uds_iy_topleft_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_ch_id) && \
+ (HIVE_ADDR_sp_ch_id != 0x3198 || \
+ HIVE_SIZE_sp_ch_id != 4)
+#error Symbol sp_ch_id occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_ch_id scalar_processor_dmem
+#define HIVE_ADDR_sp_ch_id 0x3198
+#define HIVE_SIZE_sp_ch_id 4
+#endif
+
+#if defined(HIVE_MEM_num_handled_dma_acks) && \
+ (HIVE_ADDR_num_handled_dma_acks != 0x3070 || \
+ HIVE_SIZE_num_handled_dma_acks != 4)
+#error Symbol num_handled_dma_acks occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_num_handled_dma_acks scalar_processor_dmem
+#define HIVE_ADDR_num_handled_dma_acks 0x3070
+#define HIVE_SIZE_num_handled_dma_acks 4
+#endif
+
+#if defined(HIVE_MEM__hrt_isp_css_curr_fmt_type_sp) && \
+ (HIVE_ADDR__hrt_isp_css_curr_fmt_type_sp != 0x319C || \
+ HIVE_SIZE__hrt_isp_css_curr_fmt_type_sp != 4)
+#error Symbol _hrt_isp_css_curr_fmt_type_sp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM__hrt_isp_css_curr_fmt_type_sp scalar_processor_dmem
+#define HIVE_ADDR__hrt_isp_css_curr_fmt_type_sp 0x319C
+#define HIVE_SIZE__hrt_isp_css_curr_fmt_type_sp 4
+#endif
+
+/* function isp_video_online_sp_main: 299F */
+/* function isp_copy_var_sp_main: 18B2 */
+/* function isp_xnr_var_sp_main: 3891 */
+#if defined(HIVE_MEM_sp_uds_woix) && \
+ (HIVE_ADDR_sp_uds_woix != 0x360C || \
+ HIVE_SIZE_sp_uds_woix != 4)
+#error Symbol sp_uds_woix occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix 0x360C
+#define HIVE_SIZE_sp_uds_woix 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_vblank_cycles) && \
+ (HIVE_ADDR_sp_sync_gen_vblank_cycles != 0x31A0 || \
+ HIVE_SIZE_sp_sync_gen_vblank_cycles != 4)
+#error Symbol sp_sync_gen_vblank_cycles occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_vblank_cycles scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_vblank_cycles 0x31A0
+#define HIVE_SIZE_sp_sync_gen_vblank_cycles 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_gb) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_gb != 0x3610 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_gb != 4)
+#error Symbol sp_frame_ptr_qplane_gb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_gb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_gb 0x3610
+#define HIVE_SIZE_sp_frame_ptr_qplane_gb 4
+#endif
+
+#if defined(HIVE_MEM_sp_prbs_seed) && \
+ (HIVE_ADDR_sp_prbs_seed != 0x31A4 || \
+ HIVE_SIZE_sp_prbs_seed != 4)
+#error Symbol sp_prbs_seed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_prbs_seed scalar_processor_dmem
+#define HIVE_ADDR_sp_prbs_seed 0x31A4
+#define HIVE_SIZE_sp_prbs_seed 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_x_mask) && \
+ (HIVE_ADDR_sp_tpg_x_mask != 0x31A8 || \
+ HIVE_SIZE_sp_tpg_x_mask != 4)
+#error Symbol sp_tpg_x_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_x_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_x_mask 0x31A8
+#define HIVE_SIZE_sp_tpg_x_mask 4
+#endif
+
+#if defined(HIVE_MEM_xmem_bin_addr) && \
+ (HIVE_ADDR_xmem_bin_addr != 0x31AC || \
+ HIVE_SIZE_xmem_bin_addr != 4)
+#error Symbol xmem_bin_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_xmem_bin_addr scalar_processor_dmem
+#define HIVE_ADDR_xmem_bin_addr 0x31AC
+#define HIVE_SIZE_xmem_bin_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woiy) && \
+ (HIVE_ADDR_sp_uds_woiy != 0x3614 || \
+ HIVE_SIZE_sp_uds_woiy != 4)
+#error Symbol sp_uds_woiy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woiy scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woiy 0x3614
+#define HIVE_SIZE_sp_uds_woiy 4
+#endif
+
+#if defined(HIVE_MEM_sp_fmt_type) && \
+ (HIVE_ADDR_sp_fmt_type != 0x31B0 || \
+ HIVE_SIZE_sp_fmt_type != 4)
+#error Symbol sp_fmt_type occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_fmt_type scalar_processor_dmem
+#define HIVE_ADDR_sp_fmt_type 0x31B0
+#define HIVE_SIZE_sp_fmt_type 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_v) && \
+ (HIVE_ADDR_sp_si_blend_overlay_v != 0x3618 || \
+ HIVE_SIZE_sp_si_blend_overlay_v != 4)
+#error Symbol sp_si_blend_overlay_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_v 0x3618
+#define HIVE_SIZE_sp_si_blend_overlay_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_vecs) && \
+ (HIVE_ADDR_sp_if_b_buf_vecs != 0x361C || \
+ HIVE_SIZE_sp_if_b_buf_vecs != 4)
+#error Symbol sp_if_b_buf_vecs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_vecs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_vecs 0x361C
+#define HIVE_SIZE_sp_if_b_buf_vecs 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_start_index) && \
+ (HIVE_ADDR_sp_if_a_buf_start_index != 0x3620 || \
+ HIVE_SIZE_sp_if_a_buf_start_index != 4)
+#error Symbol sp_if_a_buf_start_index occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_start_index scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_start_index 0x3620
+#define HIVE_SIZE_sp_if_a_buf_start_index 4
+#endif
+
+/* function isp_postgdc_var_sp_main: 3672 */
+#if defined(HIVE_MEM_sp_frame_ptr_plane_batr) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_batr != 0x3624 || \
+ HIVE_SIZE_sp_frame_ptr_plane_batr != 4)
+#error Symbol sp_frame_ptr_plane_batr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_batr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_batr 0x3624
+#define HIVE_SIZE_sp_frame_ptr_plane_batr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_num_chunks) && \
+ (HIVE_ADDR_sp_uds_num_chunks != 0x3628 || \
+ HIVE_SIZE_sp_uds_num_chunks != 4)
+#error Symbol sp_uds_num_chunks occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_num_chunks scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_num_chunks 0x3628
+#define HIVE_SIZE_sp_uds_num_chunks 4
+#endif
+
+#if defined(HIVE_MEM_sp_obarea_lengthBQ) && \
+ (HIVE_ADDR_sp_obarea_lengthBQ != 0x31B4 || \
+ HIVE_SIZE_sp_obarea_lengthBQ != 4)
+#error Symbol sp_obarea_lengthBQ occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_obarea_lengthBQ scalar_processor_dmem
+#define HIVE_ADDR_sp_obarea_lengthBQ 0x31B4
+#define HIVE_SIZE_sp_obarea_lengthBQ 4
+#endif
+
+#if defined(HIVE_MEM_vres_in) && \
+ (HIVE_ADDR_vres_in != 0x31B8 || \
+ HIVE_SIZE_vres_in != 4)
+#error Symbol vres_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vres_in scalar_processor_dmem
+#define HIVE_ADDR_vres_in 0x31B8
+#define HIVE_SIZE_vres_in 4
+#endif
+
+#if defined(HIVE_MEM_deci_log_factor) && \
+ (HIVE_ADDR_deci_log_factor != 0x31BC || \
+ HIVE_SIZE_deci_log_factor != 4)
+#error Symbol deci_log_factor occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_deci_log_factor scalar_processor_dmem
+#define HIVE_ADDR_deci_log_factor 0x31BC
+#define HIVE_SIZE_deci_log_factor 4
+#endif
+
+#if defined(HIVE_MEM_vres) && \
+ (HIVE_ADDR_vres != 0x31C0 || \
+ HIVE_SIZE_vres != 4)
+#error Symbol vres occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vres scalar_processor_dmem
+#define HIVE_ADDR_vres 0x31C0
+#define HIVE_SIZE_vres 4
+#endif
+
+/* function isp_primary_ds_sp_main: 1CF6 */
+#if defined(HIVE_MEM_sp_uds_bpp) && \
+ (HIVE_ADDR_sp_uds_bpp != 0x362C || \
+ HIVE_SIZE_sp_uds_bpp != 4)
+#error Symbol sp_uds_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_bpp 0x362C
+#define HIVE_SIZE_sp_uds_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_bytes_copied) && \
+ (HIVE_ADDR_sp_bin_copy_bytes_copied != 0x31C4 || \
+ HIVE_SIZE_sp_bin_copy_bytes_copied != 4)
+#error Symbol sp_bin_copy_bytes_copied occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_bytes_copied scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_bytes_copied 0x31C4
+#define HIVE_SIZE_sp_bin_copy_bytes_copied 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_eol_offset) && \
+ (HIVE_ADDR_sp_if_b_buf_eol_offset != 0x3630 || \
+ HIVE_SIZE_sp_if_b_buf_eol_offset != 4)
+#error Symbol sp_if_b_buf_eol_offset occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_eol_offset scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_eol_offset 0x3630
+#define HIVE_SIZE_sp_if_b_buf_eol_offset 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_y) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_y != 0x3634 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_y != 4)
+#error Symbol sp_uds_dma_pixel_block_width_b_in_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_y 0x3634
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_bci) && \
+ (HIVE_ADDR_sp_uds_bci != 0x3638 || \
+ HIVE_SIZE_sp_uds_bci != 4)
+#error Symbol sp_uds_bci occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_bci scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_bci 0x3638
+#define HIVE_SIZE_sp_uds_bci 4
+#endif
+
+#if defined(HIVE_MEM_isp_sh_dma_cmd_buffer) && \
+ (HIVE_ADDR_isp_sh_dma_cmd_buffer != 0x3538 || \
+ HIVE_SIZE_isp_sh_dma_cmd_buffer != 4)
+#error Symbol isp_sh_dma_cmd_buffer occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_isp_sh_dma_cmd_buffer scalar_processor_dmem
+#define HIVE_ADDR_isp_sh_dma_cmd_buffer 0x3538
+#define HIVE_SIZE_isp_sh_dma_cmd_buffer 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_bg_u) && \
+ (HIVE_ADDR_sp_overlay_bg_u != 0x31C8 || \
+ HIVE_SIZE_sp_overlay_bg_u != 4)
+#error Symbol sp_overlay_bg_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_u scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_u 0x31C8
+#define HIVE_SIZE_sp_overlay_bg_u 4
+#endif
+
+/* function _initialize_macc_coefficients: ED4 */
+#if defined(HIVE_MEM_sp_if_b_left_padding) && \
+ (HIVE_ADDR_sp_if_b_left_padding != 0x363C || \
+ HIVE_SIZE_sp_if_b_left_padding != 4)
+#error Symbol sp_if_b_left_padding occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_left_padding scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_left_padding 0x363C
+#define HIVE_SIZE_sp_if_b_left_padding 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_vertcoef_vectors) && \
+ (HIVE_ADDR_sp_sdis_vertcoef_vectors != 0x31CC || \
+ HIVE_SIZE_sp_sdis_vertcoef_vectors != 4)
+#error Symbol sp_sdis_vertcoef_vectors occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_vertcoef_vectors scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_vertcoef_vectors 0x31CC
+#define HIVE_SIZE_sp_sdis_vertcoef_vectors 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_width) && \
+ (HIVE_ADDR_sp_sync_gen_width != 0x31D0 || \
+ HIVE_SIZE_sp_sync_gen_width != 4)
+#error Symbol sp_sync_gen_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_width scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_width 0x31D0
+#define HIVE_SIZE_sp_sync_gen_width 4
+#endif
+
+#if defined(HIVE_MEM_hres) && \
+ (HIVE_ADDR_hres != 0x31D4 || \
+ HIVE_SIZE_hres != 4)
+#error Symbol hres occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_hres scalar_processor_dmem
+#define HIVE_ADDR_hres 0x31D4
+#define HIVE_SIZE_hres 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv) && \
+ (HIVE_ADDR_sp_frame_ptr_uv != 0x3640 || \
+ HIVE_SIZE_sp_frame_ptr_uv != 4)
+#error Symbol sp_frame_ptr_uv occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv 0x3640
+#define HIVE_SIZE_sp_frame_ptr_uv 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_ratb) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_ratb != 0x3644 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_ratb != 4)
+#error Symbol sp_frame_ptr_qplane_ratb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_ratb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_ratb 0x3644
+#define HIVE_SIZE_sp_frame_ptr_qplane_ratb 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_icx_left_rounded_u) && \
+ (HIVE_ADDR_sp_uds_icx_left_rounded_u != 0x3648 || \
+ HIVE_SIZE_sp_uds_icx_left_rounded_u != 4)
+#error Symbol sp_uds_icx_left_rounded_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_icx_left_rounded_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_icx_left_rounded_u 0x3648
+#define HIVE_SIZE_sp_uds_icx_left_rounded_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_y) && \
+ (HIVE_ADDR_sp_si_blend_input_y != 0x364C || \
+ HIVE_SIZE_sp_si_blend_input_y != 4)
+#error Symbol sp_si_blend_input_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_y 0x364C
+#define HIVE_SIZE_sp_si_blend_input_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv_in) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_in != 0x3650 || \
+ HIVE_SIZE_sp_frame_ptr_uv_in != 4)
+#error Symbol sp_frame_ptr_uv_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_in 0x3650
+#define HIVE_SIZE_sp_frame_ptr_uv_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_cropped_width) && \
+ (HIVE_ADDR_sp_if_a_cropped_width != 0x3654 || \
+ HIVE_SIZE_sp_if_a_cropped_width != 4)
+#error Symbol sp_if_a_cropped_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_cropped_width scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_cropped_width 0x3654
+#define HIVE_SIZE_sp_if_a_cropped_width 4
+#endif
+
+/* function isp_bayer_ds_var_sp_main: 3A35 */
+#if defined(HIVE_MEM_sp_tpg_x_delta) && \
+ (HIVE_ADDR_sp_tpg_x_delta != 0x31D8 || \
+ HIVE_SIZE_sp_tpg_x_delta != 4)
+#error Symbol sp_tpg_x_delta occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_x_delta scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_x_delta 0x31D8
+#define HIVE_SIZE_sp_tpg_x_delta 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_vertproj_num) && \
+ (HIVE_ADDR_sp_sdis_vertproj_num != 0x31DC || \
+ HIVE_SIZE_sp_sdis_vertproj_num != 4)
+#error Symbol sp_sdis_vertproj_num occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_vertproj_num scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_vertproj_num 0x31DC
+#define HIVE_SIZE_sp_sdis_vertproj_num 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_yuv420) && \
+ (HIVE_ADDR_sp_if_a_yuv420 != 0x3658 || \
+ HIVE_SIZE_sp_if_a_yuv420 != 4)
+#error Symbol sp_if_a_yuv420 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_yuv420 scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_yuv420 0x3658
+#define HIVE_SIZE_sp_if_a_yuv420 4
+#endif
+
+/* function sp_dma_proxy_run_entry: 767 */
+#ifdef HIVE_ADDR_sp_dma_proxy_run_entry
+#error Symbol sp_dma_proxy_run_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_dma_proxy_run_entry 0x767
+#endif
+
+/* function isp_primary_14mp_sp_main: 13C2 */
+#if defined(HIVE_MEM_sp_frame_ptr_bayer0) && \
+ (HIVE_ADDR_sp_frame_ptr_bayer0 != 0x365C || \
+ HIVE_SIZE_sp_frame_ptr_bayer0 != 4)
+#error Symbol sp_frame_ptr_bayer0 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_bayer0 scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_bayer0 0x365C
+#define HIVE_SIZE_sp_frame_ptr_bayer0 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_y) && \
+ (HIVE_ADDR_sp_si_blend_overlay_y != 0x3660 || \
+ HIVE_SIZE_sp_si_blend_overlay_y != 4)
+#error Symbol sp_si_blend_overlay_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_y 0x3660
+#define HIVE_SIZE_sp_si_blend_overlay_y 4
+#endif
+
+/* function isp_preview_ds_sp_main: 238F */
+#if defined(HIVE_MEM_sp_overlay_v_addr) && \
+ (HIVE_ADDR_sp_overlay_v_addr != 0x31E0 || \
+ HIVE_SIZE_sp_overlay_v_addr != 4)
+#error Symbol sp_overlay_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_v_addr 0x31E0
+#define HIVE_SIZE_sp_overlay_v_addr 4
+#endif
+
+/* function sp_dma_proxy_wait_for_ack: C72 */
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_u) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_u != 0x3664 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_u != 4)
+#error Symbol sp_uds_dma_pixel_block_width_b_in_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_u 0x3664
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_u) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_u != 0x3668 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_u != 4)
+#error Symbol sp_frame_ptr_vfout_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_u 0x3668
+#define HIVE_SIZE_sp_frame_ptr_vfout_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_gb) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_gb != 0x366C || \
+ HIVE_SIZE_sp_frame_ptr_plane_gb != 4)
+#error Symbol sp_frame_ptr_plane_gb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_gb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_gb 0x366C
+#define HIVE_SIZE_sp_frame_ptr_plane_gb 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_uv) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_uv != 0x3670 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_uv != 4)
+#error Symbol sp_frame_ptr_vfout_uv occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_uv scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_uv 0x3670
+#define HIVE_SIZE_sp_frame_ptr_vfout_uv 4
+#endif
+
+/* function initialize_lut: F56 */
+#if defined(HIVE_MEM_input_stream_format) && \
+ (HIVE_ADDR_input_stream_format != 0x31E4 || \
+ HIVE_SIZE_input_stream_format != 4)
+#error Symbol input_stream_format occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_input_stream_format scalar_processor_dmem
+#define HIVE_ADDR_input_stream_format 0x31E4
+#define HIVE_SIZE_input_stream_format 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_r) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_r != 0x3674 || \
+ HIVE_SIZE_sp_frame_ptr_plane_r != 4)
+#error Symbol sp_frame_ptr_plane_r occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_r scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_r 0x3674
+#define HIVE_SIZE_sp_frame_ptr_plane_r 4
+#endif
+
+/* function copy_frame_entry: 2CD */
+#ifdef HIVE_ADDR_copy_frame_entry
+#error Symbol copy_frame_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_copy_frame_entry 0x2CD
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_u) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_u != 0x3678 || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_u != 4)
+#error Symbol sp_frame_ptr_yuv_16_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_u 0x3678
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_u 4
+#endif
+
+#if defined(HIVE_MEM_vtmp4) && \
+ (HIVE_ADDR_vtmp4 != 0x31E8 || \
+ HIVE_SIZE_vtmp4 != 512)
+#error Symbol vtmp4 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vtmp4 scalar_processor_dmem
+#define HIVE_ADDR_vtmp4 0x31E8
+#define HIVE_SIZE_vtmp4 512
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_y_prev != 0x367C || \
+ HIVE_SIZE_sp_frame_ptr_y_prev != 4)
+#error Symbol sp_frame_ptr_y_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_prev 0x367C
+#define HIVE_SIZE_sp_frame_ptr_y_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_isp_binary_id) && \
+ (HIVE_ADDR_sp_isp_binary_id != 0x33E8 || \
+ HIVE_SIZE_sp_isp_binary_id != 4)
+#error Symbol sp_isp_binary_id occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_isp_binary_id scalar_processor_dmem
+#define HIVE_ADDR_sp_isp_binary_id 0x33E8
+#define HIVE_SIZE_sp_isp_binary_id 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_uncomp_bpp) && \
+ (HIVE_ADDR_sp_mipi_uncomp_bpp != 0x33EC || \
+ HIVE_SIZE_sp_mipi_uncomp_bpp != 4)
+#error Symbol sp_mipi_uncomp_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_uncomp_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_uncomp_bpp 0x33EC
+#define HIVE_SIZE_sp_mipi_uncomp_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_b) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_b != 0x3680 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_b != 4)
+#error Symbol sp_frame_ptr_qplane_b occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_b scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_b 0x3680
+#define HIVE_SIZE_sp_frame_ptr_qplane_b 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_out) && \
+ (HIVE_ADDR_sp_bin_copy_out != 0x33F0 || \
+ HIVE_SIZE_sp_bin_copy_out != 4)
+#error Symbol sp_bin_copy_out occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_out scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_out 0x33F0
+#define HIVE_SIZE_sp_bin_copy_out 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_r) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_r != 0x3684 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_r != 4)
+#error Symbol sp_frame_ptr_qplane_r occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_r scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_r 0x3684
+#define HIVE_SIZE_sp_frame_ptr_qplane_r 4
+#endif
+
+/* function copy_frame: 2D2 */
+#if defined(HIVE_MEM_sp_out_crop_pos_y) && \
+ (HIVE_ADDR_sp_out_crop_pos_y != 0x33F4 || \
+ HIVE_SIZE_sp_out_crop_pos_y != 4)
+#error Symbol sp_out_crop_pos_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_out_crop_pos_y scalar_processor_dmem
+#define HIVE_ADDR_sp_out_crop_pos_y 0x33F4
+#define HIVE_SIZE_sp_out_crop_pos_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_start_x) && \
+ (HIVE_ADDR_sp_overlay_start_x != 0x33F8 || \
+ HIVE_SIZE_sp_overlay_start_x != 4)
+#error Symbol sp_overlay_start_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_start_x scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_start_x 0x33F8
+#define HIVE_SIZE_sp_overlay_start_x 4
+#endif
+
+/* function isp_gdc_var_sp_main: 354E */
+#if defined(HIVE_MEM_sp_mipi_comp_bpp) && \
+ (HIVE_ADDR_sp_mipi_comp_bpp != 0x33FC || \
+ HIVE_SIZE_sp_mipi_comp_bpp != 4)
+#error Symbol sp_mipi_comp_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_comp_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_comp_bpp 0x33FC
+#define HIVE_SIZE_sp_mipi_comp_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_u) && \
+ (HIVE_ADDR_sp_frame_ptr_u != 0x3688 || \
+ HIVE_SIZE_sp_frame_ptr_u != 4)
+#error Symbol sp_frame_ptr_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u 0x3688
+#define HIVE_SIZE_sp_frame_ptr_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_online) && \
+ (HIVE_ADDR_sp_online != 0x3400 || \
+ HIVE_SIZE_sp_online != 4)
+#error Symbol sp_online occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_online scalar_processor_dmem
+#define HIVE_ADDR_sp_online 0x3400
+#define HIVE_SIZE_sp_online 4
+#endif
+
+/* function program_input_circuit: D0 */
+#if defined(HIVE_MEM_sp_vfin_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfin_c_frame_simdwidth != 0x3404 || \
+ HIVE_SIZE_sp_vfin_c_frame_simdwidth != 4)
+#error Symbol sp_vfin_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfin_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfin_c_frame_simdwidth 0x3404
+#define HIVE_SIZE_sp_vfin_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_v_addr) && \
+ (HIVE_ADDR_sp_output_v_addr != 0x3408 || \
+ HIVE_SIZE_sp_output_v_addr != 4)
+#error Symbol sp_output_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_v_addr 0x3408
+#define HIVE_SIZE_sp_output_v_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_v_in) && \
+ (HIVE_ADDR_sp_frame_ptr_v_in != 0x368C || \
+ HIVE_SIZE_sp_frame_ptr_v_in != 4)
+#error Symbol sp_frame_ptr_v_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v_in 0x368C
+#define HIVE_SIZE_sp_frame_ptr_v_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_y) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_y != 0x3690 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_y != 4)
+#error Symbol sp_frame_ptr_overlay_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_y 0x3690
+#define HIVE_SIZE_sp_frame_ptr_overlay_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_cropped_dimy) && \
+ (HIVE_ADDR_sp_frame_cropped_dimy != 0x340C || \
+ HIVE_SIZE_sp_frame_cropped_dimy != 4)
+#error Symbol sp_frame_cropped_dimy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_cropped_dimy scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_cropped_dimy 0x340C
+#define HIVE_SIZE_sp_frame_cropped_dimy 4
+#endif
+
+/* function sp_start_isp_entry: 0 */
+#ifdef HIVE_ADDR_sp_start_isp_entry
+#error Symbol sp_start_isp_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_start_isp_entry 0x0
+#endif
+
+#if defined(HIVE_MEM_sp_vfin_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfin_y_frame_simdwidth != 0x3410 || \
+ HIVE_SIZE_sp_vfin_y_frame_simdwidth != 4)
+#error Symbol sp_vfin_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfin_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfin_y_frame_simdwidth 0x3410
+#define HIVE_SIZE_sp_vfin_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_v) && \
+ (HIVE_ADDR_sp_si_bg_v != 0x3694 || \
+ HIVE_SIZE_sp_si_bg_v != 4)
+#error Symbol sp_si_bg_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_v 0x3694
+#define HIVE_SIZE_sp_si_bg_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_current_isp_program) && \
+ (HIVE_ADDR_sp_current_isp_program != 0x3174 || \
+ HIVE_SIZE_sp_current_isp_program != 4)
+#error Symbol sp_current_isp_program occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_current_isp_program scalar_processor_dmem
+#define HIVE_ADDR_sp_current_isp_program 0x3174
+#define HIVE_SIZE_sp_current_isp_program 4
+#endif
+
+/* function super_impose_offline_entry: 543 */
+#ifdef HIVE_ADDR_super_impose_offline_entry
+#error Symbol super_impose_offline_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_super_impose_offline_entry 0x543
+#endif
+
+#if defined(HIVE_MEM_sp_uds_chunk_cnt_y) && \
+ (HIVE_ADDR_sp_uds_chunk_cnt_y != 0x3698 || \
+ HIVE_SIZE_sp_uds_chunk_cnt_y != 4)
+#error Symbol sp_uds_chunk_cnt_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_chunk_cnt_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_chunk_cnt_y 0x3698
+#define HIVE_SIZE_sp_uds_chunk_cnt_y 4
+#endif
+
+/* function start_input: B5 */
+/* function sp_bin_copy: 255 */
+/* function sp_dma_proxy_configure_channel: D64 */
+/* function sp_gen_histogram_entry: 420 */
+#ifdef HIVE_ADDR_sp_gen_histogram_entry
+#error Symbol sp_gen_histogram_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_gen_histogram_entry 0x420
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_in) && \
+ (HIVE_ADDR_sp_frame_ptr_y_in != 0x369C || \
+ HIVE_SIZE_sp_frame_ptr_y_in != 4)
+#error Symbol sp_frame_ptr_y_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_in 0x369C
+#define HIVE_SIZE_sp_frame_ptr_y_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_y_addr) && \
+ (HIVE_ADDR_sp_input_y_addr != 0x3414 || \
+ HIVE_SIZE_sp_input_y_addr != 4)
+#error Symbol sp_input_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_y_addr 0x3414
+#define HIVE_SIZE_sp_input_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_horicoef_vectors) && \
+ (HIVE_ADDR_sp_sdis_horicoef_vectors != 0x3418 || \
+ HIVE_SIZE_sp_sdis_horicoef_vectors != 4)
+#error Symbol sp_sdis_horicoef_vectors occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_horicoef_vectors scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_horicoef_vectors 0x3418
+#define HIVE_SIZE_sp_sdis_horicoef_vectors 4
+#endif
+
+#if defined(HIVE_MEM_sp_obarea_startBQ) && \
+ (HIVE_ADDR_sp_obarea_startBQ != 0x341C || \
+ HIVE_SIZE_sp_obarea_startBQ != 4)
+#error Symbol sp_obarea_startBQ occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_obarea_startBQ scalar_processor_dmem
+#define HIVE_ADDR_sp_obarea_startBQ 0x341C
+#define HIVE_SIZE_sp_obarea_startBQ 4
+#endif
+
+#if defined(HIVE_MEM_sp_g_dma_vtmp) && \
+ (HIVE_ADDR_sp_g_dma_vtmp != 0x36A0 || \
+ HIVE_SIZE_sp_g_dma_vtmp != 128)
+#error Symbol sp_g_dma_vtmp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_g_dma_vtmp scalar_processor_dmem
+#define HIVE_ADDR_sp_g_dma_vtmp 0x36A0
+#define HIVE_SIZE_sp_g_dma_vtmp 128
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_left_padding) && \
+ (HIVE_ADDR_sp_if_a_left_padding != 0x3720 || \
+ HIVE_SIZE_sp_if_a_left_padding != 4)
+#error Symbol sp_if_a_left_padding occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_left_padding scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_left_padding 0x3720
+#define HIVE_SIZE_sp_if_a_left_padding 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_y) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_y != 0x3724 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_y != 4)
+#error Symbol sp_frame_ptr_vfout_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_y 0x3724
+#define HIVE_SIZE_sp_frame_ptr_vfout_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_timeout) && \
+ (HIVE_ADDR_sp_mipi_timeout != 0x3420 || \
+ HIVE_SIZE_sp_mipi_timeout != 4)
+#error Symbol sp_mipi_timeout occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_timeout scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_timeout 0x3420
+#define HIVE_SIZE_sp_mipi_timeout 4
+#endif
+
+/* function isp_video_offline_sp_main: 26B2 */
+#if defined(HIVE_MEM_sp_uds_ibuf_offset_y) && \
+ (HIVE_ADDR_sp_uds_ibuf_offset_y != 0x3728 || \
+ HIVE_SIZE_sp_uds_ibuf_offset_y != 44)
+#error Symbol sp_uds_ibuf_offset_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ibuf_offset_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ibuf_offset_y 0x3728
+#define HIVE_SIZE_sp_uds_ibuf_offset_y 44
+#endif
+
+#if defined(HIVE_MEM_sp_uds_ipx_start_array_u) && \
+ (HIVE_ADDR_sp_uds_ipx_start_array_u != 0x3754 || \
+ HIVE_SIZE_sp_uds_ipx_start_array_u != 44)
+#error Symbol sp_uds_ipx_start_array_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ipx_start_array_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ipx_start_array_u 0x3754
+#define HIVE_SIZE_sp_uds_ipx_start_array_u 44
+#endif
+
+/* function initialize_isp_xmem_base_addr_pointers: EB9 */
+#if defined(HIVE_MEM_sp_si_overlay_height) && \
+ (HIVE_ADDR_sp_si_overlay_height != 0x3780 || \
+ HIVE_SIZE_sp_si_overlay_height != 4)
+#error Symbol sp_si_overlay_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_height scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_height 0x3780
+#define HIVE_SIZE_sp_si_overlay_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_v) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_v != 0x3784 || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_v != 4)
+#error Symbol sp_frame_ptr_yuv_16_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_v 0x3784
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_y_delta) && \
+ (HIVE_ADDR_sp_tpg_y_delta != 0x3424 || \
+ HIVE_SIZE_sp_tpg_y_delta != 4)
+#error Symbol sp_tpg_y_delta occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_y_delta scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_y_delta 0x3424
+#define HIVE_SIZE_sp_tpg_y_delta 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_output_y_frame_simdwidth != 0x3428 || \
+ HIVE_SIZE_sp_output_y_frame_simdwidth != 4)
+#error Symbol sp_output_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_output_y_frame_simdwidth 0x3428
+#define HIVE_SIZE_sp_output_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_output_c_frame_simdwidth != 0x342C || \
+ HIVE_SIZE_sp_output_c_frame_simdwidth != 4)
+#error Symbol sp_output_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_output_c_frame_simdwidth 0x342C
+#define HIVE_SIZE_sp_output_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_shift) && \
+ (HIVE_ADDR_sp_si_blend_shift != 0x3788 || \
+ HIVE_SIZE_sp_si_blend_shift != 4)
+#error Symbol sp_si_blend_shift occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_shift scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_shift 0x3788
+#define HIVE_SIZE_sp_si_blend_shift 4
+#endif
+
+#if defined(HIVE_MEM__hrt_isp_css_curr_ch_id_sp) && \
+ (HIVE_ADDR__hrt_isp_css_curr_ch_id_sp != 0x3430 || \
+ HIVE_SIZE__hrt_isp_css_curr_ch_id_sp != 4)
+#error Symbol _hrt_isp_css_curr_ch_id_sp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM__hrt_isp_css_curr_ch_id_sp scalar_processor_dmem
+#define HIVE_ADDR__hrt_isp_css_curr_ch_id_sp 0x3430
+#define HIVE_SIZE__hrt_isp_css_curr_ch_id_sp 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_vecs) && \
+ (HIVE_ADDR_sp_if_a_buf_vecs != 0x378C || \
+ HIVE_SIZE_sp_if_a_buf_vecs != 4)
+#error Symbol sp_if_a_buf_vecs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_vecs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_vecs 0x378C
+#define HIVE_SIZE_sp_if_a_buf_vecs 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_width) && \
+ (HIVE_ADDR_sp_overlay_width != 0x3434 || \
+ HIVE_SIZE_sp_overlay_width != 4)
+#error Symbol sp_overlay_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_width scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_width 0x3434
+#define HIVE_SIZE_sp_overlay_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_vfout_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfout_y_frame_simdwidth != 0x3438 || \
+ HIVE_SIZE_sp_vfout_y_frame_simdwidth != 4)
+#error Symbol sp_vfout_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfout_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfout_y_frame_simdwidth 0x3438
+#define HIVE_SIZE_sp_vfout_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_mode) && \
+ (HIVE_ADDR_sp_input_mode != 0x343C || \
+ HIVE_SIZE_sp_input_mode != 4)
+#error Symbol sp_input_mode occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_mode scalar_processor_dmem
+#define HIVE_ADDR_sp_input_mode 0x343C
+#define HIVE_SIZE_sp_input_mode 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_xy_mask) && \
+ (HIVE_ADDR_sp_tpg_xy_mask != 0x3440 || \
+ HIVE_SIZE_sp_tpg_xy_mask != 4)
+#error Symbol sp_tpg_xy_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_xy_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_xy_mask 0x3440
+#define HIVE_SIZE_sp_tpg_xy_mask 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_width) && \
+ (HIVE_ADDR_sp_frame_width != 0x3444 || \
+ HIVE_SIZE_sp_frame_width != 4)
+#error Symbol sp_frame_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_width scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_width 0x3444
+#define HIVE_SIZE_sp_frame_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_vfout_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfout_c_frame_simdwidth != 0x3448 || \
+ HIVE_SIZE_sp_vfout_c_frame_simdwidth != 4)
+#error Symbol sp_vfout_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfout_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfout_c_frame_simdwidth 0x3448
+#define HIVE_SIZE_sp_vfout_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_start_y) && \
+ (HIVE_ADDR_sp_overlay_start_y != 0x344C || \
+ HIVE_SIZE_sp_overlay_start_y != 4)
+#error Symbol sp_overlay_start_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_start_y scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_start_y 0x344C
+#define HIVE_SIZE_sp_overlay_start_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_vf_crop_pos_y) && \
+ (HIVE_ADDR_sp_vf_crop_pos_y != 0x3450 || \
+ HIVE_SIZE_sp_vf_crop_pos_y != 4)
+#error Symbol sp_vf_crop_pos_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vf_crop_pos_y scalar_processor_dmem
+#define HIVE_ADDR_sp_vf_crop_pos_y 0x3450
+#define HIVE_SIZE_sp_vf_crop_pos_y 4
+#endif
+
+#if defined(HIVE_MEM_xmem_map_addr) && \
+ (HIVE_ADDR_xmem_map_addr != 0x3454 || \
+ HIVE_SIZE_xmem_map_addr != 4)
+#error Symbol xmem_map_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_xmem_map_addr scalar_processor_dmem
+#define HIVE_ADDR_xmem_map_addr 0x3454
+#define HIVE_SIZE_xmem_map_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_increment) && \
+ (HIVE_ADDR_sp_if_a_buf_increment != 0x3790 || \
+ HIVE_SIZE_sp_if_a_buf_increment != 4)
+#error Symbol sp_if_a_buf_increment occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_increment scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_increment 0x3790
+#define HIVE_SIZE_sp_if_a_buf_increment 4
+#endif
+
+#if defined(HIVE_MEM_sp_out_crop_pos_x) && \
+ (HIVE_ADDR_sp_out_crop_pos_x != 0x3458 || \
+ HIVE_SIZE_sp_out_crop_pos_x != 4)
+#error Symbol sp_out_crop_pos_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_out_crop_pos_x scalar_processor_dmem
+#define HIVE_ADDR_sp_out_crop_pos_x 0x3458
+#define HIVE_SIZE_sp_out_crop_pos_x 4
+#endif
+
+#if defined(HIVE_MEM___exit_value) && \
+ (HIVE_ADDR___exit_value != 0x0 || \
+ HIVE_SIZE___exit_value != 4)
+#error Symbol __exit_value occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM___exit_value scalar_processor_dmem
+#define HIVE_ADDR___exit_value 0x0
+#define HIVE_SIZE___exit_value 4
+#endif
+
+/* function isp_primary_var_sp_main: 1602 */
+/* function sp_gen_histogram: 425 */
+#if defined(HIVE_MEM_sp_output_y_addr) && \
+ (HIVE_ADDR_sp_output_y_addr != 0x345C || \
+ HIVE_SIZE_sp_output_y_addr != 4)
+#error Symbol sp_output_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_y_addr 0x345C
+#define HIVE_SIZE_sp_output_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_cropped_dimx) && \
+ (HIVE_ADDR_sp_frame_cropped_dimx != 0x3460 || \
+ HIVE_SIZE_sp_frame_cropped_dimx != 4)
+#error Symbol sp_frame_cropped_dimx occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_cropped_dimx scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_cropped_dimx 0x3460
+#define HIVE_SIZE_sp_frame_cropped_dimx 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_width) && \
+ (HIVE_ADDR_sp_si_overlay_width != 0x3794 || \
+ HIVE_SIZE_sp_si_overlay_width != 4)
+#error Symbol sp_si_overlay_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_width scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_width 0x3794
+#define HIVE_SIZE_sp_si_overlay_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_start_line) && \
+ (HIVE_ADDR_sp_if_a_start_line != 0x3798 || \
+ HIVE_SIZE_sp_if_a_start_line != 4)
+#error Symbol sp_if_a_start_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_start_line scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_start_line 0x3798
+#define HIVE_SIZE_sp_if_a_start_line 4
+#endif
+
+#if defined(HIVE_MEM_bayer_conf) && \
+ (HIVE_ADDR_bayer_conf != 0x138 || \
+ HIVE_SIZE_bayer_conf != 56)
+#error Symbol bayer_conf occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_bayer_conf scalar_processor_dmem
+#define HIVE_ADDR_bayer_conf 0x138
+#define HIVE_SIZE_bayer_conf 56
+#endif
+
+/* function sp_dma_proxy_write: CB0 */
+#if defined(HIVE_MEM_sp_if_block_fifo_no_reqs) && \
+ (HIVE_ADDR_sp_if_block_fifo_no_reqs != 0x379C || \
+ HIVE_SIZE_sp_if_block_fifo_no_reqs != 4)
+#error Symbol sp_if_block_fifo_no_reqs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_block_fifo_no_reqs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_block_fifo_no_reqs 0x379C
+#define HIVE_SIZE_sp_if_block_fifo_no_reqs 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_hblank_cycles) && \
+ (HIVE_ADDR_sp_sync_gen_hblank_cycles != 0x3464 || \
+ HIVE_SIZE_sp_sync_gen_hblank_cycles != 4)
+#error Symbol sp_sync_gen_hblank_cycles occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_hblank_cycles scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_hblank_cycles 0x3464
+#define HIVE_SIZE_sp_sync_gen_hblank_cycles 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_last_u) && \
+ (HIVE_ADDR_sp_uds_oxdim_last_u != 0x37A0 || \
+ HIVE_SIZE_sp_uds_oxdim_last_u != 4)
+#error Symbol sp_uds_oxdim_last_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_last_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_last_u 0x37A0
+#define HIVE_SIZE_sp_uds_oxdim_last_u 4
+#endif
+
+/* function stop_input: 9A */
+#if defined(HIVE_MEM_sp_frame_ptr_u_in) && \
+ (HIVE_ADDR_sp_frame_ptr_u_in != 0x37A4 || \
+ HIVE_SIZE_sp_frame_ptr_u_in != 4)
+#error Symbol sp_frame_ptr_u_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u_in 0x37A4
+#define HIVE_SIZE_sp_frame_ptr_u_in 4
+#endif
+
+/* function isp_vf_pp_sp_main: FBE */
+#if defined(HIVE_MEM_sp_sync_gen_height) && \
+ (HIVE_ADDR_sp_sync_gen_height != 0x3468 || \
+ HIVE_SIZE_sp_sync_gen_height != 4)
+#error Symbol sp_sync_gen_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_height scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_height 0x3468
+#define HIVE_SIZE_sp_sync_gen_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_program_input_circuit) && \
+ (HIVE_ADDR_sp_program_input_circuit != 0x346C || \
+ HIVE_SIZE_sp_program_input_circuit != 4)
+#error Symbol sp_program_input_circuit occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_program_input_circuit scalar_processor_dmem
+#define HIVE_ADDR_sp_program_input_circuit 0x346C
+#define HIVE_SIZE_sp_program_input_circuit 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_start_column) && \
+ (HIVE_ADDR_sp_if_a_start_column != 0x37A8 || \
+ HIVE_SIZE_sp_if_a_start_column != 4)
+#error Symbol sp_if_a_start_column occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_start_column scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_start_column 0x37A8
+#define HIVE_SIZE_sp_if_a_start_column 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_changed) && \
+ (HIVE_ADDR_sp_if_b_changed != 0x37AC || \
+ HIVE_SIZE_sp_if_b_changed != 4)
+#error Symbol sp_if_b_changed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_changed scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_changed 0x37AC
+#define HIVE_SIZE_sp_if_b_changed 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_y) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_y != 0x37B0 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_y != 4)
+#error Symbol sp_uds_dma_pixel_block_width_a_in_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_y 0x37B0
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_y 4
+#endif
+
+/* function isp_primary_16mp_sp_main: 1181 */
+#if defined(HIVE_MEM_sp_uds_ibuf_offset_u) && \
+ (HIVE_ADDR_sp_uds_ibuf_offset_u != 0x37B4 || \
+ HIVE_SIZE_sp_uds_ibuf_offset_u != 44)
+#error Symbol sp_uds_ibuf_offset_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ibuf_offset_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ibuf_offset_u 0x37B4
+#define HIVE_SIZE_sp_uds_ibuf_offset_u 44
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_gr) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_gr != 0x37E0 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_gr != 4)
+#error Symbol sp_frame_ptr_qplane_gr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_gr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_gr 0x37E0
+#define HIVE_SIZE_sp_frame_ptr_qplane_gr 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_bg_v) && \
+ (HIVE_ADDR_sp_overlay_bg_v != 0x3470 || \
+ HIVE_SIZE_sp_overlay_bg_v != 4)
+#error Symbol sp_overlay_bg_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_v scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_v 0x3470
+#define HIVE_SIZE_sp_overlay_bg_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_deinterleaving) && \
+ (HIVE_ADDR_sp_if_b_deinterleaving != 0x37E4 || \
+ HIVE_SIZE_sp_if_b_deinterleaving != 4)
+#error Symbol sp_if_b_deinterleaving occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_deinterleaving scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_deinterleaving 0x37E4
+#define HIVE_SIZE_sp_if_b_deinterleaving 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_u_addr) && \
+ (HIVE_ADDR_sp_output_u_addr != 0x3474 || \
+ HIVE_SIZE_sp_output_u_addr != 4)
+#error Symbol sp_output_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_u_addr 0x3474
+#define HIVE_SIZE_sp_output_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_v) && \
+ (HIVE_ADDR_sp_si_blend_input_v != 0x37E8 || \
+ HIVE_SIZE_sp_si_blend_input_v != 4)
+#error Symbol sp_si_blend_input_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_v 0x37E8
+#define HIVE_SIZE_sp_si_blend_input_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_vectors_per_line) && \
+ (HIVE_ADDR_sp_vectors_per_line != 0x3478 || \
+ HIVE_SIZE_sp_vectors_per_line != 4)
+#error Symbol sp_vectors_per_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vectors_per_line scalar_processor_dmem
+#define HIVE_ADDR_sp_vectors_per_line 0x3478
+#define HIVE_SIZE_sp_vectors_per_line 4
+#endif
+
+/* function _initialize_ispparm_from_host: F9E */
+#if defined(HIVE_MEM_sp_if_b_start_column) && \
+ (HIVE_ADDR_sp_if_b_start_column != 0x37EC || \
+ HIVE_SIZE_sp_if_b_start_column != 4)
+#error Symbol sp_if_b_start_column occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_start_column scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_start_column 0x37EC
+#define HIVE_SIZE_sp_if_b_start_column 4
+#endif
+
+/* function init_ifs: DA7 */
+/* function super_impose_offline: 548 */
+#if defined(HIVE_MEM_sp_init_isp) && \
+ (HIVE_ADDR_sp_init_isp != 0x347C || \
+ HIVE_SIZE_sp_init_isp != 4)
+#error Symbol sp_init_isp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_init_isp scalar_processor_dmem
+#define HIVE_ADDR_sp_init_isp 0x347C
+#define HIVE_SIZE_sp_init_isp 4
+#endif
+
+/* function hrt_isp_css_sp_store_isp_data: 3C04 */
+#if defined(HIVE_MEM_sp_if_b_buf_start_index) && \
+ (HIVE_ADDR_sp_if_b_buf_start_index != 0x37F0 || \
+ HIVE_SIZE_sp_if_b_buf_start_index != 4)
+#error Symbol sp_if_b_buf_start_index occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_start_index scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_start_index 0x37F0
+#define HIVE_SIZE_sp_if_b_buf_start_index 4
+#endif
+
+#if defined(HIVE_MEM_bits_per_pixel) && \
+ (HIVE_ADDR_bits_per_pixel != 0x3480 || \
+ HIVE_SIZE_bits_per_pixel != 4)
+#error Symbol bits_per_pixel occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_bits_per_pixel scalar_processor_dmem
+#define HIVE_ADDR_bits_per_pixel 0x3480
+#define HIVE_SIZE_bits_per_pixel 4
+#endif
+
+#if defined(HIVE_MEM_output_image_format) && \
+ (HIVE_ADDR_output_image_format != 0x3484 || \
+ HIVE_SIZE_output_image_format != 4)
+#error Symbol output_image_format occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_output_image_format scalar_processor_dmem
+#define HIVE_ADDR_output_image_format 0x3484
+#define HIVE_SIZE_output_image_format 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_height) && \
+ (HIVE_ADDR_sp_frame_height != 0x3488 || \
+ HIVE_SIZE_sp_frame_height != 4)
+#error Symbol sp_frame_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_height scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_height 0x3488
+#define HIVE_SIZE_sp_frame_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_chunk_cnt_u) && \
+ (HIVE_ADDR_sp_uds_chunk_cnt_u != 0x37F4 || \
+ HIVE_SIZE_sp_uds_chunk_cnt_u != 4)
+#error Symbol sp_uds_chunk_cnt_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_chunk_cnt_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_chunk_cnt_u 0x37F4
+#define HIVE_SIZE_sp_uds_chunk_cnt_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_y) && \
+ (HIVE_ADDR_sp_si_bg_y != 0x37F8 || \
+ HIVE_SIZE_sp_si_bg_y != 4)
+#error Symbol sp_si_bg_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_y 0x37F8
+#define HIVE_SIZE_sp_si_bg_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_increment) && \
+ (HIVE_ADDR_sp_if_b_buf_increment != 0x37FC || \
+ HIVE_SIZE_sp_if_b_buf_increment != 4)
+#error Symbol sp_if_b_buf_increment occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_increment scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_increment 0x37FC
+#define HIVE_SIZE_sp_if_b_buf_increment 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_deinterleaving) && \
+ (HIVE_ADDR_sp_if_a_deinterleaving != 0x3800 || \
+ HIVE_SIZE_sp_if_a_deinterleaving != 4)
+#error Symbol sp_if_a_deinterleaving occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_deinterleaving scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_deinterleaving 0x3800
+#define HIVE_SIZE_sp_if_a_deinterleaving 4
+#endif
+
+/* function sp_dma_proxy_init: C47 */
+#if defined(HIVE_MEM_sp_uds_dy) && \
+ (HIVE_ADDR_sp_uds_dy != 0x3804 || \
+ HIVE_SIZE_sp_uds_dy != 4)
+#error Symbol sp_uds_dy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dy scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dy 0x3804
+#define HIVE_SIZE_sp_uds_dy 4
+#endif
+
+/* function _init_frame_pointers: E13 */
+#if defined(HIVE_MEM_sp_overlay_bg_y) && \
+ (HIVE_ADDR_sp_overlay_bg_y != 0x348C || \
+ HIVE_SIZE_sp_overlay_bg_y != 4)
+#error Symbol sp_overlay_bg_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_y scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_y 0x348C
+#define HIVE_SIZE_sp_overlay_bg_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_histo_addr) && \
+ (HIVE_ADDR_sp_histo_addr != 0x3490 || \
+ HIVE_SIZE_sp_histo_addr != 4)
+#error Symbol sp_histo_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_histo_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_histo_addr 0x3490
+#define HIVE_SIZE_sp_histo_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_u_addr) && \
+ (HIVE_ADDR_sp_overlay_u_addr != 0x3494 || \
+ HIVE_SIZE_sp_overlay_u_addr != 4)
+#error Symbol sp_overlay_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_u_addr 0x3494
+#define HIVE_SIZE_sp_overlay_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv_tnr) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_tnr != 0x3808 || \
+ HIVE_SIZE_sp_frame_ptr_uv_tnr != 4)
+#error Symbol sp_frame_ptr_uv_tnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_tnr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_tnr 0x3808
+#define HIVE_SIZE_sp_frame_ptr_uv_tnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_u_addr) && \
+ (HIVE_ADDR_sp_input_u_addr != 0x3498 || \
+ HIVE_SIZE_sp_input_u_addr != 4)
+#error Symbol sp_input_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_u_addr 0x3498
+#define HIVE_SIZE_sp_input_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_eol_offset) && \
+ (HIVE_ADDR_sp_if_a_buf_eol_offset != 0x380C || \
+ HIVE_SIZE_sp_if_a_buf_eol_offset != 4)
+#error Symbol sp_if_a_buf_eol_offset occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_eol_offset scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_eol_offset 0x380C
+#define HIVE_SIZE_sp_if_a_buf_eol_offset 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_raw) && \
+ (HIVE_ADDR_sp_frame_ptr_raw != 0x3810 || \
+ HIVE_SIZE_sp_frame_ptr_raw != 4)
+#error Symbol sp_frame_ptr_raw occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_raw scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_raw 0x3810
+#define HIVE_SIZE_sp_frame_ptr_raw 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_u) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_u != 0x3814 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_u != 4)
+#error Symbol sp_uds_dma_pixel_block_width_a_in_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_u 0x3814
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y) && \
+ (HIVE_ADDR_sp_frame_ptr_y != 0x3818 || \
+ HIVE_SIZE_sp_frame_ptr_y != 4)
+#error Symbol sp_frame_ptr_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y 0x3818
+#define HIVE_SIZE_sp_frame_ptr_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_y_mask) && \
+ (HIVE_ADDR_sp_tpg_y_mask != 0x349C || \
+ HIVE_SIZE_sp_tpg_y_mask != 4)
+#error Symbol sp_tpg_y_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_y_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_y_mask 0x349C
+#define HIVE_SIZE_sp_tpg_y_mask 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woix_last_u) && \
+ (HIVE_ADDR_sp_uds_woix_last_u != 0x381C || \
+ HIVE_SIZE_sp_uds_woix_last_u != 4)
+#error Symbol sp_uds_woix_last_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix_last_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix_last_u 0x381C
+#define HIVE_SIZE_sp_uds_woix_last_u 4
+#endif
+
+/* function isp_preview_var_sp_main: 2073 */
+#if defined(HIVE_MEM_sp_uds_dx) && \
+ (HIVE_ADDR_sp_uds_dx != 0x3820 || \
+ HIVE_SIZE_sp_uds_dx != 4)
+#error Symbol sp_uds_dx occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dx scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dx 0x3820
+#define HIVE_SIZE_sp_uds_dx 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_tnr) && \
+ (HIVE_ADDR_sp_frame_ptr_y_tnr != 0x3824 || \
+ HIVE_SIZE_sp_frame_ptr_y_tnr != 4)
+#error Symbol sp_frame_ptr_y_tnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_tnr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_tnr 0x3824
+#define HIVE_SIZE_sp_frame_ptr_y_tnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_u_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_u_prev != 0x3828 || \
+ HIVE_SIZE_sp_frame_ptr_u_prev != 4)
+#error Symbol sp_frame_ptr_u_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u_prev 0x3828
+#define HIVE_SIZE_sp_frame_ptr_u_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_cropped_height) && \
+ (HIVE_ADDR_sp_if_b_cropped_height != 0x382C || \
+ HIVE_SIZE_sp_if_b_cropped_height != 4)
+#error Symbol sp_if_b_cropped_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_cropped_height scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_cropped_height 0x382C
+#define HIVE_SIZE_sp_if_b_cropped_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woix_last_y) && \
+ (HIVE_ADDR_sp_uds_woix_last_y != 0x3830 || \
+ HIVE_SIZE_sp_uds_woix_last_y != 4)
+#error Symbol sp_uds_woix_last_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix_last_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix_last_y 0x3830
+#define HIVE_SIZE_sp_uds_woix_last_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_g_macc_coef) && \
+ (HIVE_ADDR_sp_g_macc_coef != 0x3834 || \
+ HIVE_SIZE_sp_g_macc_coef != 512)
+#error Symbol sp_g_macc_coef occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_g_macc_coef scalar_processor_dmem
+#define HIVE_ADDR_sp_g_macc_coef 0x3834
+#define HIVE_SIZE_sp_g_macc_coef 512
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_ratb) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_ratb != 0x3A34 || \
+ HIVE_SIZE_sp_frame_ptr_plane_ratb != 4)
+#error Symbol sp_frame_ptr_plane_ratb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_ratb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_ratb 0x3A34
+#define HIVE_SIZE_sp_frame_ptr_plane_ratb 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_start_y) && \
+ (HIVE_ADDR_sp_si_overlay_start_y != 0x3A38 || \
+ HIVE_SIZE_sp_si_overlay_start_y != 4)
+#error Symbol sp_si_overlay_start_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_start_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_start_y 0x3A38
+#define HIVE_SIZE_sp_si_overlay_start_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_y) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_y != 0x3A3C || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_y != 4)
+#error Symbol sp_frame_ptr_yuv_16_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_y 0x3A3C
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_debug) && \
+ (HIVE_ADDR_sp_debug != 0x353C || \
+ HIVE_SIZE_sp_debug != 64)
+#error Symbol sp_debug occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_debug scalar_processor_dmem
+#define HIVE_ADDR_sp_debug 0x353C
+#define HIVE_SIZE_sp_debug 64
+#endif
+
+/* function isp_primary_small_sp_main: 19F7 */
+#if defined(HIVE_MEM_sp_frame_ptr_v_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_v_prev != 0x3A40 || \
+ HIVE_SIZE_sp_frame_ptr_v_prev != 4)
+#error Symbol sp_frame_ptr_v_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v_prev 0x3A40
+#define HIVE_SIZE_sp_frame_ptr_v_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_y_addr) && \
+ (HIVE_ADDR_sp_overlay_y_addr != 0x34A0 || \
+ HIVE_SIZE_sp_overlay_y_addr != 4)
+#error Symbol sp_overlay_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_y_addr 0x34A0
+#define HIVE_SIZE_sp_overlay_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_iy_topleft_y) && \
+ (HIVE_ADDR_sp_uds_iy_topleft_y != 0x3A44 || \
+ HIVE_SIZE_sp_uds_iy_topleft_y != 4)
+#error Symbol sp_uds_iy_topleft_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_iy_topleft_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_iy_topleft_y 0x3A44
+#define HIVE_SIZE_sp_uds_iy_topleft_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_port) && \
+ (HIVE_ADDR_sp_mipi_port != 0x34A4 || \
+ HIVE_SIZE_sp_mipi_port != 4)
+#error Symbol sp_mipi_port occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_port scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_port 0x34A4
+#define HIVE_SIZE_sp_mipi_port 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_start_line) && \
+ (HIVE_ADDR_sp_if_b_start_line != 0x3A48 || \
+ HIVE_SIZE_sp_if_b_start_line != 4)
+#error Symbol sp_if_b_start_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_start_line scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_start_line 0x3A48
+#define HIVE_SIZE_sp_if_b_start_line 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_u) && \
+ (HIVE_ADDR_sp_si_blend_input_u != 0x3A4C || \
+ HIVE_SIZE_sp_si_blend_input_u != 4)
+#error Symbol sp_si_blend_input_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_u 0x3A4C
+#define HIVE_SIZE_sp_si_blend_input_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_v) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_v != 0x3A50 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_v != 4)
+#error Symbol sp_frame_ptr_overlay_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_v 0x3A50
+#define HIVE_SIZE_sp_frame_ptr_overlay_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_floored_u) && \
+ (HIVE_ADDR_sp_uds_oxdim_floored_u != 0x3A54 || \
+ HIVE_SIZE_sp_uds_oxdim_floored_u != 4)
+#error Symbol sp_uds_oxdim_floored_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_floored_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_floored_u 0x3A54
+#define HIVE_SIZE_sp_uds_oxdim_floored_u 4
+#endif
+
+/* function isp_video_online_nodz_sp_main: 3072 */
+#if defined(HIVE_MEM_sp_vectors_per_input_line) && \
+ (HIVE_ADDR_sp_vectors_per_input_line != 0x34A8 || \
+ HIVE_SIZE_sp_vectors_per_input_line != 4)
+#error Symbol sp_vectors_per_input_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vectors_per_input_line scalar_processor_dmem
+#define HIVE_ADDR_sp_vectors_per_input_line 0x34A8
+#define HIVE_SIZE_sp_vectors_per_input_line 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_height) && \
+ (HIVE_ADDR_sp_overlay_height != 0x34AC || \
+ HIVE_SIZE_sp_overlay_height != 4)
+#error Symbol sp_overlay_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_height scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_height 0x34AC
+#define HIVE_SIZE_sp_overlay_height 4
+#endif
+
+#if defined(HIVE_MEM_dma_proxy_kill_req) && \
+ (HIVE_ADDR_dma_proxy_kill_req != 0x2C68 || \
+ HIVE_SIZE_dma_proxy_kill_req != 1)
+#error Symbol dma_proxy_kill_req occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_dma_proxy_kill_req scalar_processor_dmem
+#define HIVE_ADDR_dma_proxy_kill_req 0x2C68
+#define HIVE_SIZE_dma_proxy_kill_req 1
+#endif
+
+#if defined(HIVE_MEM_mem_map) && \
+ (HIVE_ADDR_mem_map != 0x3A58 || \
+ HIVE_SIZE_mem_map != 108)
+#error Symbol mem_map occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_mem_map scalar_processor_dmem
+#define HIVE_ADDR_mem_map 0x3A58
+#define HIVE_SIZE_mem_map 108
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_changed) && \
+ (HIVE_ADDR_sp_if_a_changed != 0x3AC4 || \
+ HIVE_SIZE_sp_if_a_changed != 4)
+#error Symbol sp_if_a_changed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_changed scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_changed 0x3AC4
+#define HIVE_SIZE_sp_if_a_changed 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_b) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_b != 0x3AC8 || \
+ HIVE_SIZE_sp_frame_ptr_plane_b != 4)
+#error Symbol sp_frame_ptr_plane_b occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_b scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_b 0x3AC8
+#define HIVE_SIZE_sp_frame_ptr_plane_b 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_floored_y) && \
+ (HIVE_ADDR_sp_uds_oxdim_floored_y != 0x3ACC || \
+ HIVE_SIZE_sp_uds_oxdim_floored_y != 4)
+#error Symbol sp_uds_oxdim_floored_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_floored_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_floored_y 0x3ACC
+#define HIVE_SIZE_sp_uds_oxdim_floored_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_start_x) && \
+ (HIVE_ADDR_sp_si_overlay_start_x != 0x3AD0 || \
+ HIVE_SIZE_sp_si_overlay_start_x != 4)
+#error Symbol sp_si_overlay_start_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_start_x scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_start_x 0x3AD0
+#define HIVE_SIZE_sp_si_overlay_start_x 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_cropped_width) && \
+ (HIVE_ADDR_sp_if_b_cropped_width != 0x3AD4 || \
+ HIVE_SIZE_sp_if_b_cropped_width != 4)
+#error Symbol sp_if_b_cropped_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_cropped_width scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_cropped_width 0x3AD4
+#define HIVE_SIZE_sp_if_b_cropped_width 4
+#endif
+
+#if defined(HIVE_MEM_vtmp1) && \
+ (HIVE_ADDR_vtmp1 != 0x34B0 || \
+ HIVE_SIZE_vtmp1 != 128)
+#error Symbol vtmp1 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vtmp1 scalar_processor_dmem
+#define HIVE_ADDR_vtmp1 0x34B0
+#define HIVE_SIZE_vtmp1 128
+#endif
+
+#if defined(HIVE_MEM_sp_uds_ipx_start_array_y) && \
+ (HIVE_ADDR_sp_uds_ipx_start_array_y != 0x3AD8 || \
+ HIVE_SIZE_sp_uds_ipx_start_array_y != 44)
+#error Symbol sp_uds_ipx_start_array_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ipx_start_array_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ipx_start_array_y 0x3AD8
+#define HIVE_SIZE_sp_uds_ipx_start_array_y 44
+#endif
+
+/* function isp_video_online_ds_sp_main: 2D0E */
+#if defined(HIVE_MEM_sp_uds_oxdim_last_y) && \
+ (HIVE_ADDR_sp_uds_oxdim_last_y != 0x3B04 || \
+ HIVE_SIZE_sp_uds_oxdim_last_y != 4)
+#error Symbol sp_uds_oxdim_last_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_last_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_last_y 0x3B04
+#define HIVE_SIZE_sp_uds_oxdim_last_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_2ppc) && \
+ (HIVE_ADDR_sp_2ppc != 0x3530 || \
+ HIVE_SIZE_sp_2ppc != 4)
+#error Symbol sp_2ppc occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_2ppc scalar_processor_dmem
+#define HIVE_ADDR_sp_2ppc 0x3530
+#define HIVE_SIZE_sp_2ppc 4
+#endif
+
+/* function sp_dma_proxy_run: 771 */
+/* function sp_bin_copy_entry: 250 */
+#ifdef HIVE_ADDR_sp_bin_copy_entry
+#error Symbol sp_bin_copy_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_bin_copy_entry 0x250
+#endif
+
+#endif /* _SP_MAP_H_ */
diff --git a/drivers/media/video/atomisp/include/mfldisp/to_upstream.h b/drivers/media/video/atomisp/include/mfldisp/to_upstream.h
new file mode 100644
index 0000000..bbfe9b0
--- /dev/null
+++ b/drivers/media/video/atomisp/include/mfldisp/to_upstream.h
@@ -0,0 +1,44 @@
+/*
+ * Support for Medfield Penwell Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifndef __TO_UPSTREAM_H_
+#define __TO_UPSTREAM_H_
+
+#include <linux/videodev2.h>
+
+/* Exposoure, Flash and privacy (indicator) light controls,to be upstream */
+#define V4L2_CID_CAMERA_LASTP1 (V4L2_CID_CAMERA_CLASS_BASE + 22)
+
+#define V4L2_CID_ISO_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 0)
+#define V4L2_CID_APERTURE_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 1)
+#define V4L2_CID_SS_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 2)
+#define V4L2_CID_SS_ISO_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 3)
+#define V4L2_CID_SS_APERTURE_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 4)
+#define V4L2_CID_FLASH_DELAY (V4L2_CID_CAMERA_LASTP1 + 5)
+#define V4L2_CID_FLASH_DURATION (V4L2_CID_CAMERA_LASTP1 + 6)
+
+#define V4L2_CID_FLASH_STROBE (V4L2_CID_CAMERA_LASTP1 + 17)
+#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_CAMERA_LASTP1 + 18)
+#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_CAMERA_LASTP1 + 19)
+#define V4L2_CID_TORCH_INTENSITY (V4L2_CID_CAMERA_LASTP1 + 20)
+#define V4L2_CID_INDICATOR_INTENSITY (V4L2_CID_CAMERA_LASTP1 + 21)
+
+#endif
diff --git a/drivers/media/video/atomisp/mfldisp_v4l2.c b/drivers/media/video/atomisp/mfldisp_v4l2.c
new file mode 100644
index 0000000..ec8abde
--- /dev/null
+++ b/drivers/media/video/atomisp/mfldisp_v4l2.c
@@ -0,0 +1,4303 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h> /* mfld_isp_dbg */
+#include <linux/version.h> /* mfld_isp_dbg */
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h> /* for kmalloc */
+#include <linux/mm.h> /* for GFP_ATOMIC */
+#include <linux/pci.h> /* for DMA */
+#include <linux/pm_runtime.h> /* for runtime pm */
+#include <linux/stringify.h>
+
+#include <linux/io.h> /* ioremap */
+#include <linux/uaccess.h> /* access_ok */
+#include <linux/param.h> /* access_ok */
+#include <asm/irq.h>
+#include <linux/poll.h>
+#include <linux/stddef.h>
+
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf-core.h>
+#include <media/videobuf-vmalloc.h>
+#include <linux/firmware.h>
+
+#include <asm/intel_scu_ipc.h>
+
+#include <hmm/hmm.h>
+
+/* SH header files */
+#include <css/sh_css.h>
+#include <css/sh_css_hrt.h>
+
+#include "mfldisp_v4l2.h"
+#include "mfldisp_internal.h"
+#include <mfldisp_sensor.h>
+#include "mfld_mem.h"
+#define CI_MAX_BUF_NUM 4
+#define video_num 4
+
+#define BITS_PER_PIXEL_RAW 16 /* raw type now */
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) > (b) ? (b) : (a))
+#define W_PAD 128
+
+#define MAGIC_CHECK(is, should) \
+ if (unlikely((is) != (should))) { \
+ printk(KERN_ERR "magic mismatch: %x (expected %x)\n", \
+ is, should); \
+ BUG(); \
+ }
+
+/* TODO: translate css error into v4l2 error */
+#define return_on_css_error(stat) \
+ do {\
+ sh_css_err err = (stat); \
+ if (err != sh_css_success) { \
+ mfld_isp_dbg(KERN_ERR, "Error find in %s, %d\n", \
+ __func__, __LINE__); \
+ return -EINVAL; \
+ } \
+ } while (0)
+
+#define goto_on_css_error(stat, ret, err_label) \
+ do { \
+ ret = (stat); \
+ if (ret != sh_css_success) { \
+ mfld_isp_dbg(KERN_ERR, "Error find in %s, %d\n", \
+ __func__, __LINE__); \
+ goto err_label; \
+ } \
+ } while (0)
+
+/* for v4l2_capability */
+static const char *DRIVER = "atomisp"; /* max size 15 */
+static const char *CARD = "ATOM ISP MFLD"; /* max size 31 */
+static const char *BUS_INFO = "None"; /* max size 31 */
+static const __u32 VERSION = DRIVER_VERSION;
+static int nr = -1;
+static int isp_probe;
+
+struct ci_tvnorm {
+ char *name;
+ v4l2_std_id id;
+ u32 cxiformat;
+ u32 cxoformat;
+};
+
+struct ci_format {
+ __u32 pixelformat;
+ __u8 description[32]; /* the same as struct v4l2_fmtdesc */
+};
+
+struct ci_resolution {
+ __u32 width;
+ __u32 height;
+};
+
+enum frame_state {
+ S_UNUSED = 0, /* unused */
+ S_QUEUED, /* ready to capture */
+ S_GRABBING, /* in the process of being captured */
+ S_DONE, /* finished grabbing, but not been synced yet */
+ S_ERROR, /* something bad happened while capturing */
+};
+
+struct ci_buffer {
+ struct videobuf_buffer vb;
+ struct sh_css_frame *handle;
+ struct ci_fmt *fmt;
+};
+
+static struct ci_tvnorm tvnorms[] = {
+ {
+ .name = "CI Format",
+ .id = V4L2_STD_NTSC_M,
+ .cxiformat = 0,
+ .cxoformat = 0x181f0008,
+ },
+ {
+ .name = "CI Format NULL",
+ .id = V4L2_STD_NTSC_M_JP,
+ .cxiformat = 1,
+ .cxoformat = 0x181f0008,
+ }
+};
+
+/* subdev table */
+static struct mfld_isp_subdev mfld_isp_subdev_table[] = {
+ {
+ .subdev_type = PRIMARY_CAMERA,
+ .board_info = { I2C_BOARD_INFO("smiapp", 0x10) },
+ .i2c_adapter_id = MFLD_CI_I2C_BUS_1,
+ },
+ {
+ .subdev_type = CAMERA_MOTOR,
+ .board_info = { I2C_BOARD_INFO("ad58xx", 0x0E) },
+ .i2c_adapter_id = MFLD_CI_I2C_BUS_1,
+ },
+ {
+ .subdev_type = PRIMARY_CAMERA,
+ .board_info = { I2C_BOARD_INFO("dis71430m", 0x69) },
+ .i2c_adapter_id = MFLD_CI_I2C_BUS_1,
+ },
+ {
+ .subdev_type = SECONDARY_CAMERA,
+ .board_info = { I2C_BOARD_INFO("ov2720", 0x36) },
+ .i2c_adapter_id = MFLD_CI_I2C_BUS_1,
+ },
+ {
+ .subdev_type = LED_FLASH,
+ .board_info = { I2C_BOARD_INFO("as3645a", 0x30) },
+ .i2c_adapter_id = MFLD_CI_I2C_BUS_1,
+ },
+};
+
+#define N_SUBDEV \
+ (sizeof(mfld_isp_subdev_table)/sizeof(mfld_isp_subdev_table[0]))
+
+struct ci_camera_subdev {
+ u32 type;
+ struct v4l2_subdev *camera;
+ struct v4l2_subdev *motor;
+};
+
+struct ci_fmt {
+ __u32 pixelformat;
+ __u32 depth;
+ __u32 bytesperline;
+ __u32 framesize;
+ __u32 imagesize;
+};
+
+/*
+ * ci device struct
+ */
+struct ci_device {
+ struct v4l2_device v4l2_dev;
+ struct video_device *vdev;
+ int open;
+
+ spinlock_t irqlock;
+ struct mutex mutex;
+ struct videobuf_queue capq;
+ struct ci_fmt *cap_fmt;
+ __u32 width, height;
+ struct list_head activeq;
+
+ __u32 snr_width;
+ __u32 snr_height;
+ __u32 snr_max_width;
+ __u32 snr_max_height;
+ __u32 snr_pixelformat;
+
+ struct ci_tvnorm *tvnorm;
+
+ struct sh_css_frame *vf_frame;
+ struct sh_css_frame *regular_output_frame;
+
+ enum sh_css_frame_format sh_pixelformat;
+
+ int camera_cnt;
+ int camera_curr;
+ struct ci_camera_subdev cameras[N_SUBDEV];
+ struct v4l2_subdev *flash;
+ struct v4l2_subdev *motor;
+
+ int streaming;
+
+ int run_mode;
+ int online_process;
+ int bayer_downscaling;
+
+#ifdef MFLD_ASIC
+ void __iomem *base;
+#endif
+
+ /*OSPM related */
+ uint32_t apm_reg;
+ uint16_t apm_base;
+ uint32_t ospm_base;
+
+ struct sh_css_params *isp_params;
+
+ u32 color_effect;
+ u32 gdc_cac_en;
+ u32 bad_pixel_en;
+ u32 video_dis_en;
+ u32 sc_en;
+ u32 fpn_en;
+ u32 xnr_en;
+ int false_color;
+
+ struct sh_css_isp_ee_config *ee_config;
+ struct sh_css_isp_nr_config *nr_config;
+ struct sh_css_isp_tnr_config *tnr_config;
+ struct sh_css_isp_ob_config *ob_config;
+
+ int dis_x;
+ int dis_y;
+
+ wait_queue_head_t wq_frame_complete;
+ bool frame_done;
+ sh_css_err state_frame;
+};
+
+#define _TO_CI_DEVICE(dev) container_of(dev, struct ci_device, vdev)
+
+/*
+ * input image data, and current frame resolution for test
+ */
+#define ISP_PARAM_MMAP_OFFSET 0xfffff000
+
+void __iomem *io_base;
+static struct ci_device *CI_DEV;
+struct video_device *VDEV;
+static const int vf_width = 640;
+static const int vf_height = 480;
+static const enum sh_css_frame_format vf_format = sh_css_frame_format_yuv420;
+
+struct v4l2_subdev *get_current_camera(struct ci_device *ci)
+{
+ if (ci->camera_curr < 0 || ci->camera_curr > 4)
+ return NULL;
+
+ return ci->cameras[ci->camera_curr].camera;
+}
+
+static struct mfld_ci_mipi_camera *to_sensor_mipi_info(struct v4l2_subdev *sd)
+{
+ return (struct mfld_ci_mipi_camera *)v4l2_get_subdev_hostdata(sd);
+}
+/*
+ * supported V4L2 fmts and resolutions
+ */
+static const struct ci_format SUPPORTED_FMTS[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .description = "YUV420, planner"},
+ {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .description = "YVU420, planner"},
+ {
+ .pixelformat = V4L2_PIX_FMT_YUV422P,
+ .description = "YUV422, planner"},
+ {
+ .pixelformat = V4L2_PIX_FMT_YUV444,
+ .description = "YUV444"},
+ {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .description = "NV12, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .description = "NV21, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .description = "NV16, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .description = "NV61, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .description = "YUYV, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .description = "UYVY, interleaved"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SBGGR16,
+ .description = "Bayer 16"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SBGGR8,
+ .description = "Bayer 8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SGBRG8,
+ .description = "Bayer 8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SGRBG8,
+ .description = "Bayer 8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SRGGB8,
+ .description = "Bayer 8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SBGGR10,
+ .description = "Bayer 10"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SGBRG10,
+ .description = "Bayer 10"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SGRBG10,
+ .description = "Bayer 10"},
+ {
+ .pixelformat = V4L2_PIX_FMT_SRGGB10,
+ .description = "Bayer 10"},
+ {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .description = "24 RGB 8-8-8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_RGB32,
+ .description = "32 RGB 8-8-8-8"},
+ {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .description = "16 RGB 5-6-5"}
+};
+
+static const __u32 SUPPORTED_FMT_NUM =
+sizeof(SUPPORTED_FMTS) / sizeof(SUPPORTED_FMTS[0]);
+
+struct v4l2_queryctrl ci_v4l2_controls[] = {
+ {
+ .id = V4L2_CID_AUTOGAIN,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .name = "Automatic Gain Control",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_AUTO_WHITE_BALANCE,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .name = "Automatic White Balance",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_RED_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Red Balance",
+ .minimum = 0x00,
+ .maximum = 0xff,
+ .step = 1,
+ .default_value = 0x00,
+ },
+ {
+ .id = V4L2_CID_BLUE_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Blue Balance",
+ .minimum = 0x00,
+ .maximum = 0xff,
+ .step = 1,
+ .default_value = 0x00,
+ },
+ {
+ .id = V4L2_CID_EXPOSURE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Shutter Control",
+ .minimum = 0x00,
+ .maximum = 0xff,
+ .step = 1,
+ .default_value = 0x00,
+ },
+ {
+ .id = V4L2_CID_GAIN,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Analog Gain",
+ .minimum = 0x00,
+ .maximum = 0xff,
+ .step = 1,
+ .default_value = 0x0c,
+ },
+ {
+ .id = V4L2_CID_GAMMA,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Gamma",
+ .minimum = 0x00,
+ .maximum = 0xff,
+ .step = 1,
+ .default_value = 0x00,
+ },
+ {
+ .id = V4L2_CID_HFLIP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Image h-flip",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_VFLIP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Image v-flip",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_COLORFX,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Image Color Effect",
+ .minimum = 0,
+ .maximum = 9,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Bad Pixel Correction",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "GDC/CAC",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_VIDEO_STABLIZATION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Video Stablization",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_FIXED_PATTERN_NR,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Fixed Pattern Noise Reduction",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "False Color Correction",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_ATOMISP_SHADING_CORRECTION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Lens Shading Correction",
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ }
+};
+
+static const __u32 SUPPORTED_CTRL_NUM =
+sizeof(ci_v4l2_controls) / sizeof(ci_v4l2_controls[0]);
+
+static inline void MSG_WRITE32(uint port, uint offset, u32 value);
+static inline u32 MSG_READ32(uint port, uint offset);
+
+static void enable_isp_irq(enum hrt_isp_css_irq irq,
+ bool enable)
+{
+ if (enable) {
+ sh_css_hrt_irq_enable(irq, true, false);
+ switch (irq) {
+ case hrt_isp_css_irq_sp:
+ sh_css_hrt_irq_enable_sp(true);
+ break;
+ default:
+ break;
+ }
+
+ } else {
+ sh_css_hrt_irq_disable(irq);
+ switch (irq) {
+ case hrt_isp_css_irq_sp:
+ sh_css_hrt_irq_enable_sp(false);
+ break;
+ default:
+ break;
+ }
+ }
+
+}
+
+static void clear_isp_irq(enum hrt_isp_css_irq irq)
+{
+ switch (irq) {
+ case hrt_isp_css_irq_sp:
+ sh_css_hrt_irq_clear_sp();
+ default:
+ break;
+ }
+}
+
+static void msi_irq_init(struct pci_dev *dev)
+{
+ u32 msg_ret;
+ u32 msi_address;
+ u16 msi_data;
+
+ pci_read_config_dword(dev, 0x94, &msi_address);
+ pci_read_config_word(dev, 0x98, &msi_data);
+ msi_data = msi_data & 0xffff;
+ mfld_isp_dbg(KERN_DEBUG, "msi address:0x%x, data:0x%x.\n",
+ msi_address, msi_data);
+
+ MSG_WRITE32(0x08, 0x025, msi_address);
+
+ msg_ret = MSG_READ32(0x08, 0x024);
+ msg_ret = msg_ret | 0x10000;
+ MSG_WRITE32(0x08, 0x024, msg_ret);
+
+ msg_ret = 0x1010000;
+ MSG_WRITE32(0x08, 0x027, msg_ret);
+
+ msg_ret = MSG_READ32(0x08, 0x1);
+ msg_ret = msg_ret | 0x404;
+ MSG_WRITE32(0x08, 0x1, msg_ret);
+
+ MSG_WRITE32(0x08, 0x26, msi_data);
+}
+
+static void msi_irq_uninit(struct pci_dev *dev)
+{
+ u32 msg_ret;
+
+ msg_ret = MSG_READ32(0x08, 0x024);
+ msg_ret = msg_ret & ~0x10000;
+ MSG_WRITE32(0x08, 0x024, msg_ret);
+
+ msg_ret = 0x0;
+ MSG_WRITE32(0x08, 0x027, msg_ret);
+
+ msg_ret = MSG_READ32(0x08, 0x1);
+ msg_ret = msg_ret & ~0x404;
+ MSG_WRITE32(0x08, 0x1, msg_ret);
+}
+
+static irqreturn_t atomisp_isr(int irq, void *dev)
+{
+ enum hrt_isp_css_irq hrt_irq;
+ enum hrt_isp_css_irq_status status_irq;
+ u32 msg_ret;
+ struct ci_device *ci = (struct ci_device *)dev;
+
+ do {
+ status_irq = sh_css_hrt_irq_get_id(&hrt_irq);
+ if (status_irq != hrt_isp_css_irq_status_success &&
+ status_irq != hrt_isp_css_irq_status_more_irqs) {
+ mfld_isp_dbg(KERN_ERR, "%s: err irq id!\n", __func__);
+ break;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "IRQ type:0x%x\n", hrt_irq);
+ switch (hrt_irq) {
+ case hrt_isp_css_irq_sp:
+ /* disable interrupt */
+ enable_isp_irq(hrt_isp_css_irq_sp, false);
+ /* clear flag */
+ clear_isp_irq(hrt_isp_css_irq_sp);
+ /* proc interrupt */
+ ci->state_frame =
+ start_next_binary((ShBool *)&ci->frame_done);
+ if (ci->state_frame != sh_css_success ||
+ ci->frame_done == true) {
+ wake_up_interruptible(&ci->wq_frame_complete);
+ ci->frame_done = false;
+ } else
+ /* enable interrupt */
+ enable_isp_irq(hrt_isp_css_irq_sp,
+ true);
+ break;
+ default:
+ mfld_isp_dbg(KERN_ERR,
+ "unrecognized irq type: 0x%x!\n",
+ hrt_irq);
+ }
+ } while (status_irq == hrt_isp_css_irq_status_more_irqs);
+
+ /* Clear irq reg at PENWELL B0 */
+ msg_ret = MSG_READ32(0x08, 0x027);
+ msg_ret = msg_ret | 0x10000;
+ MSG_WRITE32(0x08, 0x027, msg_ret);
+
+ return IRQ_HANDLED;
+}
+
+void *get_io_virt_addr(unsigned int address)
+{
+ unsigned int ret = 0;
+
+ ret = (unsigned int)io_base + (address & 0x003FFFFF);
+
+ return (void *)ret;
+}
+
+/*
+ * utils for buffer allocation/free
+ */
+static inline unsigned long kvirt_to_pa(void *virt)
+{
+ __u32 kva;
+
+ kva = (unsigned long)page_address(vmalloc_to_page(virt));
+ kva |= ((__u32) virt) & (PAGE_SIZE - 1); /* restore the offset */
+ return __pa(kva);
+}
+
+#define __bytes_to_pgnr_ceil(bytes) \
+ (((bytes) + ((1<<PAGE_SHIFT) - 1)) >> PAGE_SHIFT)
+
+int get_frame_pgnr(const struct sh_css_frame *frame, __u32 * p_pgnr)
+{
+ if (!frame) {
+ mfld_isp_dbg(KERN_ERR, "NULL frame pointer.\n");
+ return -EINVAL;
+ }
+
+ (*p_pgnr) = __bytes_to_pgnr_ceil(frame->data_bytes);
+ return 0;
+}
+
+/*
+ * get SH fmt according to V4L2 fmt
+ */
+static enum sh_css_frame_format v4l2_fmt_to_sh_fmt(__u32 fmt)
+{
+ switch (fmt) {
+ case V4L2_PIX_FMT_YUV420:
+ return sh_css_frame_format_yuv420;
+ case V4L2_PIX_FMT_YVU420:
+ return sh_css_frame_format_yv12;
+ case V4L2_PIX_FMT_YUV422P:
+ return sh_css_frame_format_yuv422;
+ case V4L2_PIX_FMT_YUV444:
+ return sh_css_frame_format_yuv444;
+ case V4L2_PIX_FMT_NV12:
+ return sh_css_frame_format_nv12;
+ case V4L2_PIX_FMT_NV21:
+ return sh_css_frame_format_nv21;
+ case V4L2_PIX_FMT_NV16:
+ return sh_css_frame_format_nv16;
+ case V4L2_PIX_FMT_NV61:
+ return sh_css_frame_format_nv61;
+ case V4L2_PIX_FMT_UYVY:
+ return sh_css_frame_format_uyvy;
+ case V4L2_PIX_FMT_YUYV:
+ return sh_css_frame_format_yuyv;
+ case V4L2_PIX_FMT_RGB24:
+ return sh_css_frame_format_planar_rgb888;
+ case V4L2_PIX_FMT_RGB32:
+ return sh_css_frame_format_rgba888;
+ case V4L2_PIX_FMT_RGB565:
+ return sh_css_frame_format_rgb565;
+ case V4L2_PIX_FMT_SBGGR16:
+ return sh_css_frame_format_vraw16;
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ return sh_css_frame_format_raw16;
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ return sh_css_frame_format_raw8;
+ default:
+ return -1;
+ }
+}
+
+static struct ci_format *get_ci_format(__u32 pixelformat)
+{
+ __u32 i;
+ for (i = 0; i < SUPPORTED_FMT_NUM; i++) {
+ if (SUPPORTED_FMTS[i].pixelformat == pixelformat)
+ return (struct ci_format *)(&(SUPPORTED_FMTS[i]));
+ }
+ return NULL;
+}
+
+static __u32 get_pixel_depth(__u32 pixelformat)
+{
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_YVU420:
+ return 12;
+ case V4L2_PIX_FMT_YUV422P:
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ case V4L2_PIX_FMT_RGB565:
+ case V4L2_PIX_FMT_SBGGR16:
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ return 16;
+ case V4L2_PIX_FMT_RGB24:
+ case V4L2_PIX_FMT_YUV444:
+ return 24;
+ case V4L2_PIX_FMT_RGB32:
+ return 32;
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ return 8;
+ default:
+ return 8 * 2; /* raw type now */
+ }
+}
+
+static int is_pixelformat_supported(__u32 pixelformat)
+{
+ int i;
+
+ for (i = 0; i < SUPPORTED_FMT_NUM; i++) {
+ mfld_isp_dbg(KERN_WARNING,
+ "pixel try %x, %x\n", pixelformat,
+ SUPPORTED_FMTS[i].pixelformat);
+ if (pixelformat == SUPPORTED_FMTS[i].pixelformat)
+ return 1;
+ }
+
+ return 0;
+}
+
+/* MFLD ISP feature control */
+static int mfld_isp_gdc_cac(struct ci_device *ci, int flag, __s32 * value);
+static int mfld_isp_xnr(struct ci_device *ci, int flag, int *arg)
+{
+ int xnr_enable = (*arg == 0) ? 0 : 1;
+ int gdc_enable = 1;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *arg = ci->xnr_en;
+ return 0;
+ }
+
+ if (ci->run_mode == CI_MODE_STILL_CAPTURE) {
+ if (!ci->gdc_cac_en && xnr_enable == 1)
+ mfld_isp_gdc_cac(ci, 1, &gdc_enable);
+ sh_css_capture_enable_xnr(xnr_enable);
+ }
+ return 0;
+}
+
+static int mfld_isp_bayer_nr(struct ci_device *ci, int flag,
+ struct sh_css_isp_nr_config *arg)
+{
+ const struct sh_css_isp_ee_config **default_ee_config = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (arg == NULL)
+ return -EINVAL;
+
+ /* Get nr config from current setup */
+ if (flag == 0) {
+ memcpy(arg, ci->nr_config, sizeof(struct sh_css_isp_nr_config));
+ return 0;
+ }
+
+ /* Set nr config to isp parameters */
+ sh_css_params_get_default_ee_config(default_ee_config);
+ sh_css_params_configure_nree(ci->isp_params, arg, *default_ee_config);
+ memcpy(ci->nr_config, arg, sizeof(struct sh_css_isp_nr_config));
+
+ return 0;
+}
+
+static int mfld_isp_tnr(struct ci_device *ci, int flag,
+ struct sh_css_isp_tnr_config *arg)
+{
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (arg == NULL)
+ return -EINVAL;
+
+ /* Get tnr config from current setup */
+ if (flag == 0) {
+ memcpy(arg, ci->tnr_config,
+ sizeof(struct sh_css_isp_tnr_config));
+ return 0;
+ }
+
+ if (arg->threshold_y == 0 && arg->threshold_uv == 0)
+
+ /* Set tnr config to isp parameters */
+ sh_css_params_configure_tnr(ci->isp_params, arg);
+ memcpy(ci->tnr_config, arg, sizeof(struct sh_css_isp_tnr_config));
+
+ return 0;
+}
+
+static int mfld_isp_histogram(struct ci_device *ci, int flag, void *arg)
+{
+ return 0;
+}
+
+static int mfld_isp_black_level(struct ci_device *ci, int flag,
+ struct sh_css_isp_ob_config *arg)
+{
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (arg == NULL)
+ return -EINVAL;
+
+ /* Get ob config from current setup */
+ if (flag == 0) {
+ memcpy(arg, ci->ob_config, sizeof(struct sh_css_isp_ob_config));
+ return 0;
+ }
+
+ /* Set ob config to isp parameters */
+ sh_css_params_configure_ob(ci->isp_params, arg);
+ memcpy(ci->ob_config, arg, sizeof(struct sh_css_isp_ob_config));
+
+ return 0;
+}
+
+static int mfld_isp_ycc_nr(struct ci_device *ci, int flag,
+ struct sh_css_isp_nr_config *arg)
+{
+ const struct sh_css_isp_ee_config **default_ee_config = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (arg == NULL)
+ return -EINVAL;
+
+ /* Get nr config from current setup */
+ if (flag == 0) {
+ memcpy(arg, ci->nr_config, sizeof(struct sh_css_isp_nr_config));
+ return 0;
+ }
+
+ /* Set nr config to isp parameters */
+ sh_css_params_get_default_ee_config(default_ee_config);
+ sh_css_params_configure_nree(ci->isp_params, arg, *default_ee_config);
+ memcpy(ci->nr_config, arg, sizeof(struct sh_css_isp_nr_config));
+
+ return 0;
+}
+
+static int mfld_isp_ee(struct ci_device *ci, int flag,
+ struct sh_css_isp_ee_config *arg)
+{
+ const struct sh_css_isp_nr_config **default_nr_config = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (arg == NULL)
+ return -EINVAL;
+
+ /* Get ee config from current setup */
+ if (flag == 0) {
+ memcpy(arg, ci->ee_config, sizeof(struct sh_css_isp_ee_config));
+ return 0;
+ }
+
+ /* Set ee config to isp parameters */
+ sh_css_params_get_default_nr_config(default_nr_config);
+ sh_css_params_configure_nree(ci->isp_params, *default_nr_config, arg);
+ memcpy(ci->ee_config, arg, sizeof(struct sh_css_isp_ee_config));
+ return 0;
+}
+
+static int mfld_isp_set_gamma(struct ci_device *ci, int flag,
+ struct mfld_isp_gamma_tbl *arg)
+{
+ sh_css_params_set_gamma_table(ci->isp_params, arg->gamma_table);
+ return 0;
+}
+
+static int mfld_isp_get_gamma(struct ci_device *ci, int flag,
+ struct mfld_isp_gamma_tbl *arg)
+{
+ sh_css_params_get_gamma_table(ci->isp_params, arg->gamma_table);
+ return 0;
+}
+
+static int mfld_isp_dis_stat(struct ci_device *ci, int flag,
+ struct mfld_isp_dis_config *arg)
+{
+ int width_size, height_size;
+ int error;
+ int *w_sdis_hori_proj = NULL, *w_sdis_vert_proj = NULL;
+ short *sdis_hori_coef = NULL, *sdis_vert_coef = NULL;
+ struct sh_css_grid_info info;
+
+ switch (ci->run_mode) {
+ case CI_MODE_PREVIEW:
+ sh_css_preview_get_grid_info(&info);
+ break;
+ case CI_MODE_VIDEO:
+ sh_css_video_get_grid_info(&info);
+ break;
+ default:
+ sh_css_capture_get_grid_info(&info);
+ break;
+ }
+
+ if (flag == 0) {
+ if (arg->w_sdis_vertproj_tbl == NULL ||
+ arg->w_sdis_horiproj_tbl == NULL)
+ return -EINVAL;
+
+ width_size = sh_css_num_dis_coef_types * info.width_dis
+ * sizeof(int);
+ height_size = sh_css_num_dis_coef_types * info.height_dis
+ * sizeof(int);
+ w_sdis_hori_proj = kmalloc(height_size, GFP_KERNEL);
+ if (w_sdis_hori_proj == NULL) {
+ mfld_isp_dbg(KERN_ERR, "Failed to request memory\n");
+ return -ENOMEM;
+ }
+ w_sdis_vert_proj = kmalloc(width_size, GFP_KERNEL);
+ if (w_sdis_vert_proj == NULL) {
+ mfld_isp_dbg(KERN_ERR, "Failed to request memory\n");
+ kfree(w_sdis_hori_proj);
+ return -ENOMEM;
+ }
+
+ sh_css_params_dis_get_projections(w_sdis_hori_proj,
+ w_sdis_vert_proj);
+
+ error = copy_to_user(arg->w_sdis_vertproj_tbl,
+ w_sdis_vert_proj,
+ sh_css_num_dis_coef_types * info.width_dis
+ * sizeof(int));
+
+ error = copy_to_user(arg->w_sdis_horiproj_tbl,
+ w_sdis_hori_proj,
+ sh_css_num_dis_coef_types * info.height_dis
+ * sizeof(int));
+
+ arg->dis_x = ci->dis_x;
+ arg->dis_y = ci->dis_y;
+
+ kfree(w_sdis_hori_proj);
+ kfree(w_sdis_vert_proj);
+ } else {
+ if (arg->sdis_vertcoef_tbl == NULL ||
+ arg->sdis_horicoef_tbl == NULL)
+ return -EINVAL;
+
+ width_size = sizeof(short) * sh_css_num_dis_coef_types *
+ info.dis_vertcoef_num;
+ height_size = sizeof(short) * sh_css_num_dis_coef_types *
+ info.dis_horicoef_num;
+ sh_css_params_dis_get_coefficients(&sdis_hori_coef,
+ &sdis_vert_coef);
+ error = copy_from_user(sdis_hori_coef,
+ (void __user *)arg->sdis_horicoef_tbl,
+ height_size);
+ error = copy_from_user(sdis_vert_coef,
+ (void __user *)arg->sdis_vertcoef_tbl,
+ width_size);
+
+ ci->dis_x = arg->dis_x;
+ ci->dis_y = arg->dis_y;
+ }
+ return 0;
+}
+
+static int mfld_isp_3a_stat(struct ci_device *ci, int flag,
+ struct mfld_3a_stat *arg)
+{
+ struct sh_css_grid_info info;
+ struct sh_css_isp_3a_output *output;
+ unsigned int bytes;
+ unsigned long ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag != 0)
+ return -EINVAL;
+
+ if (arg == NULL)
+ return -EINVAL;
+
+ switch (ci->run_mode) {
+ case CI_MODE_STILL_CAPTURE:
+ sh_css_capture_get_grid_info(&info);
+ break;
+ case CI_MODE_PREVIEW:
+ sh_css_preview_get_grid_info(&info);
+ break;
+ case CI_MODE_VIDEO:
+ sh_css_video_get_grid_info(&info);
+ break;
+ }
+
+ bytes =
+ info.width_3a * info.height_3a * sizeof(struct
+ sh_css_isp_3a_output);
+ output = kmalloc(bytes, GFP_KERNEL);
+
+ sh_css_params_3a_get_statistics(output);
+ ret = copy_to_user(arg->w_3a_stat, output, bytes);
+ if (ret)
+ mfld_isp_dbg(KERN_DEBUG,
+ "copy to user failed copied %lu bytes\n", ret);
+
+#ifdef CI_ISP_DEBUG
+ int i;
+ /*for (i = 0; i < info.width_3a * info.height_3a; i++) { */
+ for (i = 0; i < 10; i++) {
+ struct sh_css_isp_3a_output *pt;
+ pt = output + i * sizeof(struct sh_css_isp_3a_output);
+ mfld_isp_dbg(KERN_DEBUG, "Get 3A stat from kernel %d\n", i);
+ mfld_isp_dbg(KERN_DEBUG, "ae_y = %d\n", pt->ae_Y);
+ mfld_isp_dbg(KERN_DEBUG, "awb_cnt = %d\n", pt->awb_cnt);
+ mfld_isp_dbg(KERN_DEBUG, "awb_GR = %d\n", pt->awb_GR);
+ mfld_isp_dbg(KERN_DEBUG, "awb_R = %d\n", pt->awb_R);
+ mfld_isp_dbg(KERN_DEBUG, "awb_B = %d\n", pt->awb_B);
+ mfld_isp_dbg(KERN_DEBUG, "awb_GB = %d\n", pt->awb_GB);
+ mfld_isp_dbg(KERN_DEBUG, "af_hpf1 = %d\n", pt->af_hpf1);
+ mfld_isp_dbg(KERN_DEBUG, "af_hpf2 = %d\n", pt->af_hpf2);
+ }
+#endif
+ kfree(output);
+ return 0;
+}
+
+static int mfld_isp_param(struct ci_device *ci, int flag,
+ struct mfld_isp_parm *arg)
+{
+ struct sh_css_grid_info *info;
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+
+ /* Read parameter for 3A bianry info */
+ if (flag == 0) {
+ if (&arg->info == NULL) {
+ mfld_isp_dbg(KERN_ERR, "NULL pointer in grid_info\n");
+ return -EINVAL;
+ }
+
+ info = &arg->info;
+ switch (ci->run_mode) {
+ case CI_MODE_STILL_CAPTURE:
+ sh_css_capture_get_grid_info(info);
+ break;
+ case CI_MODE_PREVIEW:
+ sh_css_preview_get_grid_info(info);
+ break;
+ case CI_MODE_VIDEO:
+ sh_css_video_get_grid_info(info);
+ break;
+ }
+ return 0;
+ }
+
+ sh_css_params_configure_wb(ci->isp_params, &arg->wb_config);
+ sh_css_params_configure_cc(ci->isp_params, &arg->cc_config);
+ sh_css_params_configure_ob(ci->isp_params, &arg->ob_config);
+ sh_css_params_configure_dp(ci->isp_params, &arg->dp_config);
+ sh_css_params_configure_nree(ci->isp_params, &arg->nr_config,
+ &arg->ee_config);
+ sh_css_params_configure_tnr(ci->isp_params, &arg->tnr_config);
+#ifdef CI_ISP_DEBUG
+ struct sh_css_isp_wb_config *wb_config = &arg->wb_config;
+ struct sh_css_isp_cc_config *cc_config = &arg->cc_config;
+ struct sh_css_isp_ob_config *ob_config = &arg->ob_config;
+ mfld_isp_dbg(KERN_DEBUG, "wb: gr = %x, r = %x, b = %x, gb = %x\n",
+ wb_config->gr, wb_config->r,
+ wb_config->b, wb_config->gb);
+ mfld_isp_dbg(KERN_DEBUG, "CC matrix, %d, %d, %d, %d, %d, %d\n",
+ cc_config->matrix[0], cc_config->matrix[1],
+ cc_config->matrix[2], cc_config->matrix[3],
+ cc_config->matrix[4], cc_config->matrix[5]);
+ mfld_isp_dbg(KERN_DEBUG, "OB: gr %x, r %x, b %x, gb %x\n",
+ ob_config->level_gr, ob_config->level_r,
+ ob_config->level_b, ob_config->level_gb);
+#endif
+ return 0;
+}
+
+static const struct sh_css_isp_cc_config sepia_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {141, 18, 68, -40, -5, -19, 35, 4, 16},
+};
+
+static const struct sh_css_isp_cc_config nega_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, 374, 342, 0, 672, -301},
+};
+
+static const struct sh_css_isp_cc_config mono_cc_config = {
+ .fraction_bits = 8,
+ .matrix = {255, 29, 120, 0, 0, 0, 0, 0, 0},
+};
+
+static const short skin_macc_table[] = {
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192,
+ 8192, 4096, 0, 6144, 7168, 2048, -1024, 4096, 6144, 0, 4096, 8192, 4096,
+ -1024, 2048, 7168,
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192,
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192
+};
+
+static const short blue_macc_table[] = {
+ 24576, -16384, 0, 16384, 24576, -16384, 8192, 0, 8192, 0, 0, 8192, 8192,
+ 0, 0, 8192,
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192,
+ 24576, 0, 0, 24576, 32767, 16384, -8192, 8192, 8192, 0, 0, 8192, 24576,
+ 8192, -16384, 0,
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192
+};
+
+static const short green_macc_table[] = {
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192,
+ 16384, 16384, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 0,
+ 8192,
+ 8192, 0, 0, 8192, 8192, 0, 0, 8192, 8192, 0, 16384, 16384, 8192, 0, 0,
+ 8192,
+ 16384, 16384, 0, 24576, 20480, 8192, -4096, 32767, 24576, 0, 16384,
+ 16384, 32767, -4096, 8192, 20480
+};
+
+static unsigned short vivid_ctc_table[] = {
+ 0, 0, 0
+};
+
+static int mfld_isp_color_effect(struct ci_device *ci, int flag, __s32 *effect)
+{
+ const struct sh_css_isp_cc_config *cc_config = NULL;
+ const short *macc_table = NULL;
+ const unsigned short *ctc_table = NULL;
+ const short *default_macc_table[1];
+ const struct sh_css_isp_cc_config *default_cc_config[1];
+ const unsigned short *default_ctc_table[1];
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *effect = ci->color_effect;
+ return 0;
+ }
+
+ if (*effect == ci->color_effect)
+ return 0;
+
+ switch (*effect) {
+ case V4L2_COLORFX_NONE:
+ sh_css_params_get_default_macc_table(default_macc_table);
+ sh_css_params_get_default_cc_config(default_cc_config);
+ sh_css_params_get_default_ctc_table(default_ctc_table);
+ cc_config = *default_cc_config;
+ macc_table = *default_macc_table;
+ ctc_table = *default_ctc_table;
+ break;
+ case V4L2_COLORFX_SEPIA:
+ cc_config = (const struct sh_css_isp_cc_config *)
+ &sepia_cc_config;
+ break;
+ case V4L2_COLORFX_NEGATIVE:
+ cc_config = &nega_cc_config;
+ break;
+ case V4L2_COLORFX_BW:
+ cc_config = &mono_cc_config;
+ break;
+ case V4L2_COLORFX_SKY_BLUE:
+ macc_table = blue_macc_table;
+ break;
+ case V4L2_COLORFX_GRASS_GREEN:
+ macc_table = green_macc_table;
+ break;
+ case V4L2_COLORFX_SKIN_WHITEN:
+ macc_table = skin_macc_table;
+ break;
+ case V4L2_COLORFX_VIVID:
+ ctc_table = vivid_ctc_table;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (cc_config)
+ sh_css_params_configure_cc(ci->isp_params, cc_config);
+ if (macc_table)
+ sh_css_params_set_macc_table(ci->isp_params, macc_table);
+ if (ctc_table)
+ sh_css_params_set_ctc_table(ci->isp_params,
+ (unsigned short *)ctc_table);
+ ci->color_effect = (u32)*effect;
+ return 0;
+}
+
+static int mfld_isp_bad_pixel(struct ci_device *ci, int flag, __s32 *value)
+{
+ struct sh_css_isp_dp_config dp_config;
+ const struct sh_css_isp_dp_config **default_dp_config = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *value = ci->bad_pixel_en;
+ return 0;
+ }
+
+ if (*value == ci->bad_pixel_en)
+ return 0;
+
+ if (*value) {
+ sh_css_params_get_default_dp_config(default_dp_config);
+ memcpy(&dp_config, *default_dp_config,
+ (sizeof(default_dp_config)));
+ } else {
+ dp_config.threshold = 0xFFFF;
+ dp_config.gain = 0xFFFF;
+ }
+
+ sh_css_params_configure_dp(ci->isp_params, &dp_config);
+ ci->bad_pixel_en = (*value == 0) ? 0 : 1;
+
+ return 0;
+}
+
+static int mfld_isp_gdc_cac(struct ci_device *ci, int flag, __s32 * value)
+{
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *value = ci->gdc_cac_en;
+ return 0;
+ }
+
+ if (ci->run_mode == CI_MODE_STILL_CAPTURE) {
+ sh_css_capture_set_mode(sh_css_capture_mode_advanced);
+ ci->gdc_cac_en = (*value == 0) ? 0 : 1;
+ }
+
+ return 0;
+}
+
+static int mfld_isp_video_stable(struct ci_device *ci, int flag, __s32 * value)
+{
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *value = ci->video_dis_en;
+ return 0;
+ }
+
+ if (ci->run_mode == CI_MODE_VIDEO)
+ ci->video_dis_en = (*value == 0) ? 0 : 1;
+
+ return 0;
+}
+
+static int mfld_isp_fixed_pattern(struct ci_device *ci, int flag, __s32 * value)
+{
+ struct sh_css_frame *raw_black_frame = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *value = ci->fpn_en;
+ return 0;
+ }
+
+ if (*value == 0) {
+ /*ci->isp_params->isp_parameters.fpn_enabled = 0;*/
+ ci->fpn_en = 0;
+ return 0;
+ }
+
+ /* Add function to get black from from sensor with shutter off */
+ sh_css_params_set_black_frame(ci->isp_params, raw_black_frame);
+ ci->fpn_en = 1;
+ return 0;
+}
+
+static int mfld_isp_false_color(struct ci_device *ci, int flag, __s32 * value)
+{
+ const struct sh_css_isp_de_config *default_de_config[1];
+ struct sh_css_isp_de_config de_config;
+ /* Get nr config from current setup */
+ if (flag == 0) {
+ *value = ci->false_color;
+ return 0;
+ }
+
+ /* Set nr config to isp parameters */
+ sh_css_params_get_default_de_config(default_de_config);
+ memcpy(&de_config, *default_de_config,
+ sizeof(struct sh_css_isp_de_config));
+ de_config.pixelnoise = *value;
+ sh_css_params_configure_de(ci->isp_params, &de_config);
+ ci->false_color = *value;
+ return 0;
+}
+
+static int mfld_isp_shading_correction(struct ci_device *ci, int flag,
+ __s32 *value)
+{
+ struct mfld_ci_mipi_camera *mipi_info;
+ struct sh_css_shading_table* (*shading_table_func)
+ (unsigned int frame_width,
+ unsigned int frame_height,
+ unsigned int table_width,
+ unsigned int table_height) = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ *value = ci->sc_en;
+ return 0;
+ }
+
+ if (*value == 0) {
+ sh_css_set_get_shading_table(NULL);
+ ci->sc_en = 0;
+ return 0;
+ }
+
+ /* set the shading table function */
+ mipi_info = to_sensor_mipi_info(ci->cameras[ci->camera_curr].camera);
+ shading_table_func = mipi_info->get_shading_table;
+ sh_css_set_get_shading_table(shading_table_func);
+ ci->sc_en = 1;
+ return 0;
+}
+
+static int mfld_isp_digital_zoom(struct ci_device *ci, int flag, __s32 * value)
+{
+ u32 zoom;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ if (flag == 0) {
+ sh_css_get_zoom_factor(&zoom, &zoom);
+ *value = 64 - zoom;
+ }
+
+ if (*value < 0)
+ return -EINVAL;
+
+ if (ci->run_mode == CI_MODE_VIDEO) {
+ zoom = *value;
+ if (zoom >= 64)
+ zoom = 64;
+ zoom = 64 - zoom;
+ sh_css_set_zoom_factor(zoom, zoom);
+ }
+ return 0;
+}
+
+/*
+ * v4l2 ioctls
+ */
+static int mfld_isp_querycap(struct file *file, void *fh,
+ struct v4l2_capability *cap)
+{
+ int ret = 0;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_querycaps\n");
+
+ memset(cap, 0, sizeof(struct v4l2_capability));
+ strncpy(cap->driver, DRIVER, strlen(DRIVER));
+ strncpy(cap->card, CARD, strlen(CARD));
+ strncpy(cap->bus_info, BUS_INFO, strlen(BUS_INFO));
+ cap->version = VERSION;
+
+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+
+ return ret;
+}
+
+static int mfld_isp_g_chip_ident(struct file *file, void *fh,
+ struct v4l2_dbg_chip_ident *chip)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret = 0;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ core, g_chip_ident, chip);
+ if (ret)
+ mfld_isp_dbg(KERN_ERR, "failed to s_fmt for sensor\n");
+ return ret;
+}
+
+static int mfld_isp_cropcap(struct file *file, void *fh,
+ struct v4l2_cropcap *cropcap)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_mbus_framefmt snr_mbus_fmt;
+ struct v4l2_format snr_fmt;
+ int ret;
+
+ if (cropcap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupport v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ cropcap->bounds.left = 0;
+ cropcap->bounds.top = 0;
+
+#if (!defined(IMAGE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ snr_mbus_fmt.code = V4L2_MBUS_FMT_FIXED;
+ snr_mbus_fmt.height = MFLD_ISP_MAX_HEIGHT_TMP;
+ snr_mbus_fmt.width = MFLD_ISP_MAX_WIDTH_TMP;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, try_mbus_fmt, &snr_mbus_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "failed to try_mbus_fmt for sensor"
+ ", try try_fmt\n");
+
+ snr_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ snr_fmt.fmt.pix.height = MFLD_ISP_MAX_HEIGHT_TMP;
+ snr_fmt.fmt.pix.width = MFLD_ISP_MAX_WIDTH_TMP;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, try_fmt, &snr_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR,
+ "failed to try_fmt for sensor\n");
+ return ret;
+ }
+ cropcap->bounds.width = snr_fmt.fmt.pix.width;
+ cropcap->bounds.height = snr_fmt.fmt.pix.height;
+ ci->snr_max_width = snr_fmt.fmt.pix.width;
+ ci->snr_max_height = snr_fmt.fmt.pix.height;
+ ci->snr_pixelformat = snr_fmt.fmt.pix.pixelformat;
+ } else {
+ cropcap->bounds.width = snr_mbus_fmt.width;
+ cropcap->bounds.height = snr_mbus_fmt.height;
+ ci->snr_max_width = snr_mbus_fmt.width;
+ ci->snr_max_height = snr_mbus_fmt.height;
+ ci->snr_pixelformat = snr_mbus_fmt.code;
+ }
+#else
+ cropcap->bounds.width = MFLD_ISP_MAX_WIDTH;
+ cropcap->bounds.height = MFLD_ISP_MAX_HEIGHT;
+#endif
+
+ memcpy(&cropcap->defrect, &cropcap->bounds, sizeof(struct v4l2_rect));
+ cropcap->pixelaspect.numerator = 1;
+ cropcap->pixelaspect.denominator = 1;
+ return 0;
+}
+
+static int mfld_isp_g_crop(struct file *file, void *fh,
+ struct v4l2_crop *crop)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupport v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ crop->c.left = 0;
+ crop->c.top = 0;
+
+ if (ci->bayer_downscaling) {
+ crop->c.width = ci->snr_max_width;
+ crop->c.height = ci->snr_max_height;
+ } else {
+ crop->c.width = 0;
+ crop->c.height = 0;
+ }
+
+ return 0;
+}
+
+static int mfld_isp_s_crop(struct file *file, void *fh,
+ struct v4l2_crop *crop)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_mbus_framefmt snr_mbus_fmt;
+ struct v4l2_format snr_fmt;
+ int ret;
+
+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupport v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ if (!ci->bayer_downscaling) {
+#if (!defined(IMAGoE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ snr_mbus_fmt.code = V4L2_MBUS_FMT_FIXED;
+ snr_mbus_fmt.height = MFLD_ISP_MAX_HEIGHT_TMP;
+ snr_mbus_fmt.width = MFLD_ISP_MAX_WIDTH_TMP;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, s_mbus_fmt, &snr_mbus_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR,
+ "failed to s_mbus_fmt for sensor\n");
+ snr_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ snr_fmt.fmt.pix.height = MFLD_ISP_MAX_HEIGHT;
+ snr_fmt.fmt.pix.width = MFLD_ISP_MAX_WIDTH;
+
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ video, s_fmt, &snr_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR,
+ "failed to s_fmt for sensor\n");
+ return ret;
+ }
+ ci->snr_max_width = snr_fmt.fmt.pix.width;
+ ci->snr_max_height = snr_fmt.fmt.pix.height;
+ } else {
+ ci->snr_max_width = snr_mbus_fmt.width;
+ ci->snr_max_height = snr_mbus_fmt.height;
+ }
+#else
+ ci->snr_max_width = MFLD_ISP_MAX_WIDTH_TMP;
+ ci->snr_max_height = MFLD_ISP_MAX_HEIGHT_TMP;
+#endif
+ ci->bayer_downscaling = 1;
+ }
+ return 0;
+}
+
+static int mfld_isp_enum_input(struct file *file, void *fh,
+ struct v4l2_input *input)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_enum_input\n");
+
+ if (input->index)
+ return -EINVAL;
+
+ if (!ci->cameras[input->index].camera)
+ return -EINVAL;
+
+ memset(input, 0, sizeof(struct v4l2_input));
+ strcpy(input->name, ci->cameras[input->index].camera->name);
+ input->type = V4L2_INPUT_TYPE_CAMERA;
+
+ return 0;
+}
+
+static int mfld_isp_g_input(struct file *file, void *fh, unsigned int *input)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_g_input\n");
+
+ *input = ci->camera_curr;
+
+ return 0;
+}
+
+static int mfld_isp_s_input(struct file *file, void *fh, unsigned int input)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_subdev *camera = NULL;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_s_input\n");
+
+ if (input < 0 || input > 2 || input > ci->camera_cnt)
+ return -EINVAL;
+
+ camera = ci->cameras[input].camera;
+ if (!camera)
+ return -EINVAL;
+
+ if (ci->capq.streaming == 1) {
+ mfld_isp_dbg(KERN_ERR, "ISP is still streaming, stop first\n");
+ return -EINVAL;
+ }
+
+ ci->camera_curr = input;
+
+ return 0;
+}
+
+static int mfld_isp_g_std(struct file *file, void *fh, v4l2_std_id * id)
+{
+ return -1;
+}
+
+static int mfld_isp_s_std(struct file *file, void *fh, v4l2_std_id * id)
+{
+ return -1;
+}
+
+static int mfld_isp_enum_fmt_cap(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ __u32 index = f->index;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_enum_fmt_cap\n");
+
+ /* check buf index */
+ if (index >= SUPPORTED_FMT_NUM) {
+ mfld_isp_dbg(KERN_ERR, "fmt index extends maxiumn"
+ " supported fmts number\n");
+ return -EINVAL;
+ }
+ /* check buf type */
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupported v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ f->pixelformat = SUPPORTED_FMTS[index].pixelformat;
+ memset(f->description, 0, sizeof(char)*32);
+ strncpy(f->description, SUPPORTED_FMTS[index].description,
+ strlen(SUPPORTED_FMTS[index].description));
+
+ return 0;
+}
+
+static int mfld_isp_g_fmt_cap(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_g_fmt_cap\n");
+
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupported v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ memset(f, 0, sizeof(struct v4l2_format));
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+ if (ci->width != 0) { /* VIDIOC_S_FMT already called,
+ return fmt setted by app */
+ f->fmt.pix.width = ci->width;
+ f->fmt.pix.height = ci->height;
+ f->fmt.pix.pixelformat = ci->cap_fmt->pixelformat;
+ f->fmt.pix.bytesperline = ci->cap_fmt->bytesperline;
+ f->fmt.pix.sizeimage = ci->cap_fmt->imagesize;
+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
+ } else { /* otherwise return default value */
+ f->fmt.pix.width = 640;
+ f->fmt.pix.height = 480;
+ f->fmt.pix.pixelformat = SUPPORTED_FMTS[0].pixelformat;
+ f->fmt.pix.bytesperline =
+ get_pixel_depth(f->fmt.pix.pixelformat) *
+ f->fmt.pix.width;
+ f->fmt.pix.sizeimage = f->fmt.pix.height *
+ f->fmt.pix.bytesperline;
+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
+ }
+
+ return 0;
+}
+
+
+/* This function looks up the closest available resolution. */
+static int mfld_isp_try_fmt_cap(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_mbus_framefmt snr_mbus_fmt;
+ __u32 out_width = f->fmt.pix.width;
+ __u32 out_height = f->fmt.pix.height;
+ __u32 pixelformat = f->fmt.pix.pixelformat;
+ __u32 in_width = 0;
+ __u32 in_height = 0;
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "Wrong v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "request: (wxh:%d*%d), format %x\n",
+ out_width, out_height, pixelformat);
+
+#if (!defined(IMAGE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ if (get_current_camera(ci) == NULL)
+ return -EINVAL;
+
+ snr_mbus_fmt.code = V4L2_MBUS_FMT_FIXED;
+ snr_mbus_fmt.height = out_height;
+ snr_mbus_fmt.width = out_width;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, try_mbus_fmt, &snr_mbus_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "failed to try_mbus_fmt for sensor\n");
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, try_fmt, f);
+ if (ret)
+ return ret;
+ in_width = f->fmt.pix.width;
+ in_height = f->fmt.pix.height;
+ } else {
+ in_width = snr_mbus_fmt.width;
+ in_height = snr_mbus_fmt.height;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "return snr_try_fmt, (wxh: %d*%d)\n",
+ in_width, in_height);
+#endif
+ if ((in_width < out_width) &&
+ (in_height < out_height)) {
+ out_width = in_width;
+ out_height = in_height;
+ }
+
+ if (out_width < MFLD_ISP_STEP_WIDTH ||
+ out_height < MFLD_ISP_STEP_HEIGHT)
+ return -EINVAL;
+
+ out_width = (out_width & ~(MFLD_ISP_STEP_WIDTH - 1));
+ out_height = (out_height & ~(MFLD_ISP_STEP_HEIGHT - 1));
+
+ mfld_isp_dbg(KERN_DEBUG, "Restrict width %d, height %d\n",
+ out_width, out_height);
+
+ f->fmt.pix.width = out_width;
+ f->fmt.pix.height = out_height;
+
+ if (!is_pixelformat_supported(pixelformat)) {
+ mfld_isp_dbg(KERN_ERR, "unsupported pixelformat!\n");
+ /* only support 1 pixelformat now */
+ pixelformat = SUPPORTED_FMTS[0].pixelformat;
+ }
+ f->fmt.pix.pixelformat = pixelformat;
+
+ return 0;
+}
+
+static int mfld_isp_s_fmt_cap(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct mfld_ci_mipi_camera *mipi_info;
+ struct sh_css_frame_info output_info, raw_output_info;
+ struct v4l2_mbus_framefmt snr_mbus_fmt;
+ struct v4l2_format snr_fmt;
+ __u32 width = f->fmt.pix.width;
+ __u32 height = f->fmt.pix.height;
+ __u32 pixelformat = f->fmt.pix.pixelformat;
+ __u32 effective_input_width;
+ __u32 effective_input_height;
+ __u32 pad_width = 8;
+ __u32 pad_height = 10;
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+ mfld_isp_dbg(KERN_INFO, "set: %d * %d\n", width, height);
+
+ if ((f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (f->type != V4L2_BUF_TYPE_PRIVATE)) {
+ mfld_isp_dbg(KERN_ERR, "Wrong v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ /* Set online processing */
+ if (f->type == V4L2_BUF_TYPE_PRIVATE)
+ ci->online_process = 0;
+ else
+ ci->online_process = 1;
+
+ if (!ci->bayer_downscaling) {
+#if (!defined(IMAGE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ v4l2_fill_mbus_format(&snr_mbus_fmt, &f->fmt.pix,
+ V4L2_MBUS_FMT_FIXED);
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_SBGGR16:
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ pad_width = 0;
+ pad_height = 0;
+ }
+ snr_mbus_fmt.height += pad_height;
+ snr_mbus_fmt.width += pad_width;
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, s_mbus_fmt, &snr_mbus_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR,
+ "call s_mbus_fmt for sensor failed\n");
+
+ snr_fmt = *f;
+ snr_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_SBGGR16:
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ pad_width = 0;
+ pad_height = 0;
+ }
+ snr_fmt.fmt.pix.height += pad_height;
+ snr_fmt.fmt.pix.width += pad_width;
+
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ video, s_fmt, &snr_fmt);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR,
+ "call s_fmt for sensor failed\n");
+ return ret;
+ }
+ ci->snr_width = snr_fmt.fmt.pix.width;
+ ci->snr_height = snr_fmt.fmt.pix.height;
+ ci->snr_pixelformat = snr_fmt.fmt.pix.pixelformat;
+ } else {
+ ci->snr_width = snr_mbus_fmt.width;
+ ci->snr_height = snr_mbus_fmt.height;
+ ci->snr_pixelformat = snr_mbus_fmt.code;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG,
+ "snr_width %d, snr_height %d, pixelfmt %d\n",
+ ci->snr_width, ci->snr_height,
+ ci->snr_pixelformat);
+
+ if (ci->snr_width < MFLD_ISP_STEP_WIDTH ||
+ ci->snr_height < MFLD_ISP_STEP_HEIGHT)
+ return -EINVAL;
+#endif
+ } else {
+ ci->snr_width = ci->snr_max_width;
+ ci->snr_height = ci->snr_max_height;
+ }
+
+ width = (width & ~(MFLD_ISP_STEP_WIDTH - 1));
+ height = (height & ~(MFLD_ISP_STEP_HEIGHT - 1));
+
+#if (!defined(IMAGE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ if ((ci->snr_width < width) &&
+ (ci->snr_height < height)) {
+ width = ci->snr_width;
+ height = ci->snr_height;
+ }
+
+ if (((ci->snr_width - 8) > width) &&
+ ((ci->snr_height - 10) > height) &&
+ (ci->bayer_downscaling)) {
+ mfld_isp_dbg(KERN_DEBUG, "Enable Bayer Downscaling\n");
+ effective_input_width = ci->snr_width - 8;
+ effective_input_height = ci->snr_height - 10;
+
+ /*effective_input_width = 1280;*/
+ /*effective_input_height = 720;*/
+ } else {
+ effective_input_width = width;
+ effective_input_height = height;
+ }
+#endif
+
+ ci->cap_fmt->pixelformat = pixelformat;
+ ci->sh_pixelformat = v4l2_fmt_to_sh_fmt(pixelformat);
+
+#ifdef IMAGE_FROM_FILE
+ mfld_isp_dbg(KERN_DEBUG, "alloc IMAGE data for ISP test.\n");
+ mfld_isp_dbg(KERN_DEBUG,
+ "The size we expect %d\n", ci->width * ci->height * 2);
+ mfld_isp_dbg(KERN_INFO, "The size we got %d\n", g_input_file_size);
+ ci->image_file = g_input_file_data;
+ if (!ci->image_file) {
+ mfld_isp_dbg(KERN_ERR, "Load image file failed.\n");
+ return -1;
+ }
+ if ((ci->width < IMAGE_W) && (ci->height < IMAGE_H)) {
+ ci->input_file = vmalloc(ci->width * ci->height * 2);
+ if (!ci->input_file) {
+ mfld_isp_dbg(KERN_ERR,
+ "Failed to alloc input_file memory\n");
+ return -1;
+ }
+
+ mfld_isp_resize_image((unsigned short *)ci->image_file,
+ (unsigned short *)ci->input_file, 0, 0,
+ IMAGE_W, IMAGE_H, ci->width, ci->height);
+ }
+#endif
+
+#if (!defined(IMAGE_FROM_FILE) && !defined(IMAGE_FROM_TPG))
+ mfld_isp_dbg(KERN_DEBUG, "snr_width %d, snr_height %d\n",
+ ci->snr_width, ci->snr_height);
+ sh_css_input_set_resolution(ci->snr_width, ci->snr_height);
+
+ mfld_isp_dbg(KERN_DEBUG, "Setup sensor specifc configure for MIPI\n");
+ mipi_info = to_sensor_mipi_info(ci->cameras[ci->camera_curr].camera);
+ if (mipi_info) {
+ mfld_isp_dbg(KERN_DEBUG,
+ "MIPI info from camera sensor: bayer %d"
+ " format %d\n", mipi_info->raw_bayer_order,
+ mipi_info->input_format);
+ mfld_isp_dbg(KERN_DEBUG, "sensor mipilane - %d\n",
+ mipi_info->num_of_lane);
+ sh_css_input_set_bayer_order(mipi_info->raw_bayer_order);
+ sh_css_input_set_format(mipi_info->input_format);
+ sh_css_input_configure_port(mipi_info->port,
+ mipi_info->num_of_lane,
+ 0xffff4);
+
+ } else {
+ /*sh_css_input_set_bayer_order(sh_css_bayer_order_rggb);*/
+ mfld_isp_dbg(KERN_DEBUG, "no sensor config info\n");
+ sh_css_input_set_bayer_order(sh_css_bayer_order_bggr);
+ /*sh_css_input_set_bayer_order(sh_css_bayer_order_grbg); */
+ sh_css_input_set_format(sh_css_input_format_raw_10);
+#ifdef MIPI_LANE_4
+ mfld_isp_dbg(KERN_DEBUG, "MIPI 4 lane\n");
+ sh_css_input_configure_port(sh_css_mipi_port_4lane, 4, 0xffff4);
+#endif
+#ifdef MIPI_LANE_2
+ mfld_isp_dbg(KERN_INFO, "MIPI 2 lane\n");
+ sh_css_input_configure_port(sh_css_mipi_port_4lane, 2, 0xffff4);
+#endif
+#ifdef MIPI_LANE_1
+ mfld_isp_dbg(KERN_INFO, "MIPI 1 lane\n");
+ sh_css_input_configure_port(sh_css_mipi_port_4lane, 1, 0xffff4);
+#endif
+ }
+#else
+ sh_css_input_set_resolution(width, height);
+
+#endif
+
+ return_on_css_error(sh_css_input_set_effective_resolution
+ (effective_input_width, effective_input_height));
+
+ switch (ci->run_mode) {
+ case CI_MODE_PREVIEW:
+ return_on_css_error(sh_css_preview_configure_output
+ (width, height, ci->sh_pixelformat));
+ return_on_css_error(sh_css_preview_set_isp_parameters
+ (ci->isp_params));
+ return_on_css_error(sh_css_preview_get_output_frame_info
+ (&output_info));
+ break;
+ case CI_MODE_VIDEO:
+ return_on_css_error(sh_css_video_configure_viewfinder
+ (vf_width, vf_height, vf_format));
+ return_on_css_error(sh_css_video_configure_output
+ (width, height, ci->sh_pixelformat));
+ return_on_css_error(sh_css_video_set_isp_parameters
+ (ci->isp_params));
+ return_on_css_error(sh_css_video_get_output_frame_info
+ (&output_info));
+ break;
+ default:
+#ifdef GDC_EN
+ sh_css_capture_set_mode(sh_css_capture_mode_advanced);
+#endif
+
+#ifdef XNR_EN
+ sh_css_capture_enable_xnr(1);
+#endif
+
+ if (ci->sh_pixelformat == sh_css_frame_format_vraw16 ||
+ ci->sh_pixelformat == sh_css_frame_format_raw16 ||
+ ci->sh_pixelformat == sh_css_frame_format_raw8) {
+ mfld_isp_dbg(KERN_WARNING, "set capture raw mode\n");
+ return_on_css_error(sh_css_capture_set_mode
+ (sh_css_capture_mode_raw));
+ }
+
+ return_on_css_error(sh_css_capture_enable_online
+ (ci->online_process));
+
+ return_on_css_error(sh_css_capture_configure_viewfinder
+ (vf_width, vf_height, vf_format));
+ return_on_css_error(sh_css_capture_configure_output
+ (width, height, ci->sh_pixelformat));
+ return_on_css_error(sh_css_capture_set_isp_parameters
+ (ci->isp_params));
+
+ return_on_css_error(sh_css_capture_get_output_frame_info
+ (&output_info));
+
+ if (!ci->online_process)
+ return_on_css_error
+ (sh_css_capture_get_output_raw_frame_info
+ (&raw_output_info));
+
+ if (ci->run_mode != CI_MODE_STILL_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR,
+ "Need to set the running mode first\n");
+ ci->run_mode = CI_MODE_STILL_CAPTURE;
+ }
+ break;
+ }
+
+ ci->width = width;
+ ci->height = height;
+
+ mutex_lock(&ci->capq.vb_lock);
+
+ ci->cap_fmt->pixelformat = f->fmt.pix.pixelformat;
+ ci->cap_fmt->depth = get_pixel_depth(pixelformat);
+ ci->cap_fmt->bytesperline =
+ (ci->cap_fmt->depth * output_info.padded_width) / 8;
+ ci->cap_fmt->framesize = height * ci->cap_fmt->bytesperline;
+ ci->cap_fmt->imagesize = PAGE_ALIGN(ci->cap_fmt->framesize);
+ if (f->fmt.pix.field == V4L2_FIELD_ANY)
+ f->fmt.pix.field = V4L2_FIELD_NONE;
+ ci->capq.field = f->fmt.pix.field;
+
+ mutex_unlock(&ci->capq.vb_lock);
+
+ f->fmt.pix.sizeimage = ci->cap_fmt->imagesize;
+ f->fmt.pix.width = width;
+ f->fmt.pix.height = height;
+ mfld_isp_dbg(KERN_DEBUG, "raw width %d, raw height %d\n",
+ raw_output_info.padded_width, raw_output_info.height);
+ f->fmt.pix.priv = PAGE_ALIGN(ci->width * ci->height * 2);
+
+ mfld_isp_dbg(KERN_DEBUG, "width = %d, height = %d, fourcc = %s\n",
+ ci->width, ci->height,
+ get_ci_format(ci->cap_fmt->pixelformat)->description);
+
+ mfld_isp_dbg(KERN_DEBUG, "pixeldepth = %d, frame_size = %d\n",
+ ci->cap_fmt->depth, ci->cap_fmt->framesize);
+ mfld_isp_dbg(KERN_DEBUG, "raw size priv = %d\n", f->fmt.pix.priv);
+ return 0;
+}
+
+static struct ci_resolution SUPPORTED_RESOLUTIONS[] = {
+ {.width = 4352, .height = 3264},
+ {.width = 3280, .height = 2464},
+ {.width = 3576, .height = 2016},
+ {.width = 1920, .height = 1080},
+ {.width = 1280, .height = 720},
+ {.width = 640, .height = 480}
+};
+static const __u32 SUPPORTED_RESOLUTION_NUM =
+sizeof(SUPPORTED_RESOLUTIONS) / sizeof(SUPPORTED_RESOLUTIONS[0]);
+
+static int mfld_isp_enum_framesizes(struct file *file, void *fh,
+ struct v4l2_frmsizeenum *arg)
+{
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_enum_framesizes\n");
+
+
+ if (arg->index < 0 || arg->index >= SUPPORTED_RESOLUTION_NUM)
+ return -EINVAL;
+
+ if (!is_pixelformat_supported(arg->pixel_format))
+ return -EINVAL;
+
+ arg->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+ arg->discrete.width = SUPPORTED_RESOLUTIONS[arg->index].width;
+ arg->discrete.height = SUPPORTED_RESOLUTIONS[arg->index].height;
+
+ return 0;
+}
+
+static int is_resolution_supported(__u32 width, __u32 height)
+{
+ int i;
+
+ mfld_isp_dbg(KERN_INFO,
+ "SUPPORTED_RESOLUTION_NUM: %d\n",
+ SUPPORTED_RESOLUTION_NUM);
+ for (i = 0; i < SUPPORTED_RESOLUTION_NUM; i++) {
+ if (width == SUPPORTED_RESOLUTIONS[i].width &&
+ height == SUPPORTED_RESOLUTIONS[i].height)
+ return 1;
+ }
+
+ return 0;
+}
+
+static int mfld_isp_enum_frameintervals(struct file *file, void *fh,
+ struct v4l2_frmivalenum *arg)
+{
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_enum_frameintervals\n");
+
+ if (arg->index < 0 || arg->index >= SUPPORTED_RESOLUTION_NUM)
+ return -EINVAL;
+
+ if (!is_pixelformat_supported(arg->pixel_format))
+ return -EINVAL;
+
+ if (!is_resolution_supported(arg->width, arg->height))
+ return -EINVAL;
+
+ arg->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+ arg->discrete.numerator = 1;
+ arg->discrete.denominator = 30;
+
+ return 0;
+}
+
+static int mfld_isp_reqbufs(struct file *file, void *fh,
+ struct v4l2_requestbuffers *req)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret = 0, i = 0;
+ struct sh_css_frame_info out_info, vf_info;
+ struct sh_css_frame *frame;
+ struct videobuf_vmalloc_memory *vm_mem;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_reqbufs %d\n", req->count);
+
+ switch (ci->run_mode) {
+ case CI_MODE_STILL_CAPTURE:
+ if (ci->sh_pixelformat != sh_css_frame_format_vraw16 &&
+ ci->sh_pixelformat != sh_css_frame_format_raw8 &&
+ ci->sh_pixelformat != sh_css_frame_format_raw16) {
+ goto_on_css_error
+ (sh_css_capture_get_viewfinder_frame_info
+ (&vf_info), ret, error);
+ goto_on_css_error
+ (sh_css_frame_allocate_from_info
+ (&ci->vf_frame, &vf_info), ret,
+ error);
+ }
+ goto_on_css_error(sh_css_capture_get_output_frame_info
+ (&out_info), ret, error);
+ break;
+ case CI_MODE_VIDEO:
+ goto_on_css_error(sh_css_video_get_viewfinder_frame_info
+ (&vf_info), ret, error);
+ goto_on_css_error(sh_css_video_get_output_frame_info(&out_info),
+ ret, error);
+ goto_on_css_error(sh_css_frame_allocate_from_info
+ (&ci->vf_frame, &vf_info), ret, error);
+ break;
+ case CI_MODE_PREVIEW:
+ goto_on_css_error(sh_css_preview_get_output_frame_info
+ (&out_info), ret, error);
+ break;
+ }
+
+ ret = videobuf_reqbufs(&ci->capq, req);
+ if (ret)
+ return ret;
+
+ /*
+ * for user pointer type, buffers are not really allcated here,
+ * buffers are setup in QBUF operation through v4l2_buffer structure
+ */
+ if (req->memory == V4L2_MEMORY_USERPTR) {
+ mfld_isp_dbg(KERN_DEBUG, "user pointer, not really allocate"
+ " memory here.\n");
+ return 0;
+ }
+
+ for (i = 0; i < req->count; i++) {
+ mfld_isp_dbg(KERN_ERR, "%s, %d\n", __func__, __LINE__);
+ goto_on_css_error(sh_css_frame_allocate_from_info(&frame,
+ &out_info),
+ ret, error);
+ vm_mem = ci->capq.bufs[i]->priv;
+ vm_mem->vmalloc = frame;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "request buffer done\n");
+
+ return ret;
+
+error:
+ while (i--) {
+ vm_mem = ci->capq.bufs[i]->priv;
+ sh_css_frame_free(vm_mem->vmalloc);
+ }
+ return ret;
+}
+
+static int mfld_isp_querybuf(struct file *file, void *fh,
+ struct v4l2_buffer *buf)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_querybuf: index = %d\n", buf->index);
+
+ return videobuf_querybuf(&ci->capq, buf);
+}
+
+static int mfld_isp_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ unsigned long userptr = buf->m.userptr;
+ struct videobuf_buffer *vb = ci->capq.bufs[buf->index];
+ struct videobuf_vmalloc_memory *vm_mem = vb->priv;
+ struct sh_css_frame_info out_info;
+ struct sh_css_frame *handle = NULL;
+ __u32 length;
+ __u32 pgnr;
+ int ret = 0;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_qbuf\n");
+
+ ret = videobuf_qbuf(&ci->capq, buf);
+ if (ret)
+ return ret;
+
+ if (buf->memory == V4L2_MEMORY_USERPTR) {
+ length = vb->bsize;
+ pgnr = (length + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+
+ if (vm_mem->vmalloc)
+ return 0;
+
+ switch (ci->run_mode) {
+ case CI_MODE_STILL_CAPTURE:
+ ret = sh_css_capture_get_output_frame_info(&out_info);
+ break;
+ case CI_MODE_PREVIEW:
+ ret = sh_css_preview_get_output_frame_info(&out_info);
+ break;
+ case CI_MODE_VIDEO:
+ ret = sh_css_video_get_output_frame_info(&out_info);
+ break;
+ }
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "get_output_frame_info error\n");
+ return -1;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "%s, %d\n", __func__, __LINE__);
+ hrt_isp_css_mm_set_user_ptr(userptr, pgnr);
+ sh_css_frame_allocate_from_info(&handle, &out_info);
+ hrt_isp_css_mm_set_user_ptr(0, 0);
+ if (IS_ERR(handle)) {
+ mfld_isp_dbg(KERN_ERR, "Error to allocate"
+ " frame for userptr capture %ld\n",
+ PTR_ERR(handle));
+ return PTR_ERR(handle);
+ }
+
+ vm_mem->vmalloc = handle;
+ }
+
+ return 0;
+}
+
+static int mfld_isp_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct videobuf_vmalloc_memory *vm_mem;
+ struct videobuf_buffer *vb;
+ unsigned int dvs_envelope_w, dvs_envelope_h;
+ struct sh_css_frame *raw_frame;
+ u32 msg_ret;
+ u32 term_en_count;
+ int ret;
+ unsigned long flags = 0;
+ long timeout;
+ unsigned int irq_st;
+
+ DEFINE_WAIT(_wait);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_dqbuf\n");
+
+ spin_lock_irqsave(&ci->irqlock, flags);
+ if (list_empty(&ci->activeq)) {
+ mfld_isp_dbg(KERN_ERR, "No buffer to be dequeued\n");
+ return -EINVAL;
+ }
+ vb = list_entry(ci->activeq.next, struct videobuf_buffer, queue);
+ list_del(&vb->queue);
+ spin_unlock_irqrestore(&ci->irqlock, flags);
+
+ /*
+ * Kai:
+ *
+ * setup output_frame here.
+ */
+ vm_mem = vb->priv;
+ ci->regular_output_frame = vm_mem->vmalloc;
+
+#ifdef PUNIT_CAMERA_BUSY
+ u32 msg_ret;
+ /* Set camera_busy bit in Punit */
+ msg_ret = MSG_READ32(0x04, 0x72);
+ msg_ret |= 0x100;
+ MSG_WRITE32(0x04, 0x72, msg_ret);
+#endif
+ /* for 4-lane configuration */
+ msg_ret = MSG_READ32(0x09, 0x3);
+ term_en_count = (msg_ret & 0x00f00000) >> 20;
+ mfld_isp_dbg(KERN_DEBUG, "MSG_RET = %x, TERM_EN_COUNT = %x\n",
+ msg_ret, term_en_count);
+ if (term_en_count != 0xF) {
+ term_en_count = 0xF;
+ msg_ret = (msg_ret & 0xff0fffff) |
+ ((term_en_count & 0xf) << 20);
+ MSG_WRITE32(0x09, 0x3, msg_ret);
+ }
+
+ /* for 1-lane configuration */
+ msg_ret = MSG_READ32(0x09, 0x3);
+ term_en_count = (msg_ret & 0x000f0000) >> 16;
+ mfld_isp_dbg(KERN_DEBUG, "MSG_RET = %x, TERM_EN_COUNT = %x\n",
+ msg_ret, term_en_count);
+ if (term_en_count != 0xF) {
+ term_en_count = 0xF;
+ msg_ret = (msg_ret & 0xfff0ffff) |
+ ((term_en_count & 0xf) << 16);
+ MSG_WRITE32(0x09, 0x3, msg_ret);
+ }
+
+
+ switch (ci->run_mode) {
+ case CI_MODE_STILL_CAPTURE:
+ sh_css_capture_start(ci->regular_output_frame, ci->vf_frame);
+ break;
+ case CI_MODE_PREVIEW:
+ sh_css_preview_start(ci->regular_output_frame);
+ break;
+ /*case CI_MODE_VIDEO: */
+ /*sh_css_video_start(NULL, ci->regular_output_frame,
+ * ci->vf_frame); */
+ /*break; */
+ }
+
+ if (ci->run_mode == CI_MODE_VIDEO) {
+ if (ci->video_dis_en) {
+ dvs_envelope_w = ci->width / 10;
+ dvs_envelope_h = ci->height / 10;
+ sh_css_video_set_dis_vector(ci->dis_x, ci->dis_y);
+ sh_css_video_set_dis_envelope(dvs_envelope_w,
+ dvs_envelope_h);
+ }
+ sh_css_video_start(NULL, ci->regular_output_frame,
+ ci->vf_frame);
+ }
+
+ prepare_to_wait(&ci->wq_frame_complete, &_wait, TASK_INTERRUPTIBLE);
+ enable_isp_irq(hrt_isp_css_irq_sp, true);
+ mfld_isp_dbg(KERN_DEBUG, "%s: wait frame.\n", __func__);
+ timeout = schedule_timeout(5 * HZ);
+ if (!timeout) {
+ mfld_isp_dbg(KERN_ERR, "%s: ISP timeout!\n", __func__);
+ vb->state = VIDEOBUF_ERROR;
+ finish_wait(&ci->wq_frame_complete, &_wait);
+
+ /* check css_receiver state */
+ irq_st = sh_css_hrt_receiver_get_interrupt_status(
+ sh_css_mipi_port_4lane);
+ mfld_isp_dbg(KERN_EMERG, "atomisp: 4lane css_receiver_irq_status is %x\n",
+ irq_st);
+
+ irq_st = sh_css_hrt_receiver_get_interrupt_status(
+ sh_css_mipi_port_1lane);
+ mfld_isp_dbg(KERN_EMERG, "atomisp: 1lane css_receiver_irq_status is %x\n",
+ irq_st);
+
+ return -EINVAL;
+ }
+ finish_wait(&ci->wq_frame_complete, &_wait);
+ mfld_isp_dbg(KERN_DEBUG, "%s: finished frame.\n", __func__);
+
+ if (ci->online_process == 0) {
+ raw_frame = sh_css_get_raw_frame();
+ mfld_isp_dbg(KERN_ERR, "The RAW virtual address is %x\n",
+ (unsigned int)raw_frame);
+ sh_css_convert_raw_frame(raw_frame, ci->width,
+ (ci->height + 8));
+ }
+
+ vb->field_count++;
+ vb->state = VIDEOBUF_DONE;
+
+ ret = videobuf_dqbuf(&ci->capq, buf, file->f_flags & O_NONBLOCK);
+ if (ret)
+ return ret;
+ buf->bytesused = ci->cap_fmt->framesize;
+
+#ifdef PUNIT_CAMERA_BUSY
+ /* Free camera_busy bit */
+ msg_ret = MSG_READ32(0x04, 0x72);
+ msg_ret &= ~0x100;
+ MSG_WRITE32(0x04, 0x72, msg_ret);
+#endif
+
+ return 0;
+}
+
+static int mfld_isp_streamon(struct file *file, void *fh,
+ enum v4l2_buf_type type)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_streamon\n");
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupported v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ ret = videobuf_streamon(&ci->capq);
+ if (ret)
+ return ret;
+
+#if (!defined(IMAGE_FROM_TPG))
+ mfld_isp_dbg(KERN_DEBUG, "Stream on camera sensor\n");
+ /* stream on the sensor */
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ video, s_stream, 1);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "stream on sensor err.\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int mfld_isp_streamoff(struct file *file, void *fh,
+ enum v4l2_buf_type type)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_streamoff\n");
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupported v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ ret = videobuf_streamoff(&ci->capq);
+ if (ret)
+ return ret;
+
+#if (!defined(IMAGE_FROM_TPG))
+ v4l2_subdev_call(ci->cameras[ci->camera_curr].camera, video,
+ s_stream, 0);
+#endif
+
+ return 0;
+}
+
+static int mfld_isp_g_ctrl(struct file *file, void *fh,
+ struct v4l2_control *control)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int i, ret = -EINVAL;
+
+ for (i = 0; i < SUPPORTED_CTRL_NUM; i++) {
+ if (ci_v4l2_controls[i].id == control->id) {
+ ret = 0;
+ goto next;
+ }
+ }
+
+next:
+ if (ret)
+ return ret;
+
+ switch (control->id) {
+ case V4L2_CID_GAIN:
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ core, s_ctrl, control);
+ case V4L2_CID_COLORFX:
+ ret = mfld_isp_color_effect(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION:
+ ret = mfld_isp_bad_pixel(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC:
+ ret = mfld_isp_gdc_cac(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_VIDEO_STABLIZATION:
+ ret = mfld_isp_video_stable(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_FIXED_PATTERN_NR:
+ ret = mfld_isp_fixed_pattern(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION:
+ ret = mfld_isp_false_color(ci, 0, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_SHADING_CORRECTION:
+ ret = mfld_isp_shading_correction(ci, 0, &control->value);
+ break;
+ }
+
+ /* Right now we leave this contrl function null */
+ control->value = 0;
+ return ret;
+}
+
+static int mfld_isp_s_ctrl(struct file *file, void *fh,
+ struct v4l2_control *control)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int i, ret = -EINVAL;
+
+ for (i = 0; i < SUPPORTED_CTRL_NUM; i++) {
+ if (ci_v4l2_controls[i].id == control->id) {
+ ret = 0;
+ goto next;
+ }
+ }
+
+next:
+ if (ret)
+ return ret;
+
+ switch (control->id) {
+ case V4L2_CID_COLORFX:
+ ret = mfld_isp_color_effect(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION:
+ ret = mfld_isp_bad_pixel(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC:
+ ret = mfld_isp_gdc_cac(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_VIDEO_STABLIZATION:
+ ret = mfld_isp_video_stable(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_FIXED_PATTERN_NR:
+ ret = mfld_isp_fixed_pattern(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION:
+ ret = mfld_isp_false_color(ci, 1, &control->value);
+ break;
+ case V4L2_CID_ATOMISP_SHADING_CORRECTION:
+ ret = mfld_isp_shading_correction(ci, 1, &control->value);
+ break;
+ }
+ /* Right now we leave this contrl function null */
+ return ret;
+}
+
+static int mfld_isp_queryctl(struct file *file, void *fh,
+ struct v4l2_queryctrl *qc)
+{
+ int i;
+ int ret = -EINVAL;
+
+ if (qc->id & V4L2_CTRL_FLAG_NEXT_CTRL)
+ return ret;
+
+ for (i = 0; i < SUPPORTED_CTRL_NUM; i++) {
+ if (ci_v4l2_controls[i].id == qc->id) {
+ memcpy(qc, &ci_v4l2_controls[i],
+ sizeof(struct v4l2_queryctrl));
+ qc->reserved[0] = 0;
+ qc->flags = V4L2_CTRL_FLAG_DISABLED;
+ ret = 0;
+ goto exit;
+ }
+ }
+exit:
+ return ret;
+}
+
+static int mfld_isp_camera_g_ext_ctrls(struct file *file, void *fh,
+ struct v4l2_ext_controls *c)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_control ctrl;
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < c->count; i++) {
+ ctrl.id = c->controls[i].id;
+ ctrl.value = c->controls[i].value;
+ switch (ctrl.id) {
+ case V4L2_CID_EXPOSURE_ABSOLUTE:
+ case V4L2_CID_ISO_ABSOLUTE:
+ case V4L2_CID_APERTURE_ABSOLUTE:
+ case V4L2_CID_SS_EXPOSURE_ABSOLUTE:
+ case V4L2_CID_SS_ISO_ABSOLUTE:
+ case V4L2_CID_SS_APERTURE_ABSOLUTE:
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ core, g_ctrl, &ctrl);
+ break;
+ case V4L2_CID_FOCUS_ABSOLUTE:
+ case V4L2_CID_FOCUS_AUTO:
+ if (ci->motor)
+ ret = v4l2_subdev_call(ci->motor,
+ core, g_ctrl,
+ &ctrl);
+ else
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ core, g_ctrl,
+ &ctrl);
+ break;
+ case V4L2_CID_FLASH_DELAY:
+ case V4L2_CID_FLASH_DURATION:
+ case V4L2_CID_FLASH_STROBE:
+ case V4L2_CID_FLASH_TIMEOUT:
+ case V4L2_CID_FLASH_INTENSITY:
+ case V4L2_CID_TORCH_INTENSITY:
+ case V4L2_CID_INDICATOR_INTENSITY:
+ if (ci->flash)
+ ret = v4l2_subdev_call(ci->flash,
+ core, g_ctrl,
+ &ctrl);
+ break;
+ case V4L2_CID_ZOOM_ABSOLUTE:
+ /* add digital zoom code here */
+ ret = mfld_isp_digital_zoom(ci, 0, &ctrl.value);
+ break;
+ default:
+ ret = -1;
+ }
+
+ if (ret) {
+ c->error_idx = i;
+ break;
+ }
+ c->controls[i].value = ctrl.value;
+ }
+ return ret;
+}
+
+static int mfld_isp_g_ext_ctrls(struct file *file, void *fh,
+ struct v4l2_ext_controls *c)
+{
+ struct v4l2_control ctrl;
+ int i;
+ int ret = 0;
+
+ if (c->ctrl_class == V4L2_CTRL_CLASS_USER) {
+ for (i = 0; i < c->count; i++) {
+ ctrl.id = c->controls[i].id;
+ ctrl.value = c->controls[i].value;
+ ret = mfld_isp_g_ctrl(file, fh, &ctrl);
+ c->controls[i].value = ctrl.value;
+ if (ret) {
+ c->error_idx = i;
+ break;
+ }
+ }
+ return ret;
+ }
+
+ if (c->ctrl_class == V4L2_CTRL_CLASS_CAMERA)
+ return mfld_isp_camera_g_ext_ctrls(file, fh, c);
+
+ return -EINVAL;
+}
+
+static int mfld_isp_camera_s_ext_ctrls(struct file *file, void *fh,
+ struct v4l2_ext_controls *c)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ struct v4l2_control ctrl;
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < c->count; i++) {
+ ctrl.id = c->controls[i].id;
+ ctrl.value = c->controls[i].value;
+ switch (ctrl.id) {
+ case V4L2_CID_EXPOSURE_ABSOLUTE:
+ case V4L2_CID_ISO_ABSOLUTE:
+ case V4L2_CID_APERTURE_ABSOLUTE:
+ case V4L2_CID_SS_EXPOSURE_ABSOLUTE:
+ case V4L2_CID_SS_ISO_ABSOLUTE:
+ case V4L2_CID_SS_APERTURE_ABSOLUTE:
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ core, s_ctrl, &ctrl);
+ break;
+ case V4L2_CID_FOCUS_ABSOLUTE:
+ case V4L2_CID_FOCUS_AUTO:
+ if (ci->motor)
+ ret = v4l2_subdev_call(ci->motor,
+ core, s_ctrl,
+ &ctrl);
+ else
+ ret = v4l2_subdev_call(ci->cameras
+ [ci->camera_curr].camera,
+ core, s_ctrl,
+ &ctrl);
+ break;
+ case V4L2_CID_FLASH_DELAY:
+ case V4L2_CID_FLASH_DURATION:
+ case V4L2_CID_FLASH_STROBE:
+ case V4L2_CID_FLASH_TIMEOUT:
+ case V4L2_CID_FLASH_INTENSITY:
+ case V4L2_CID_TORCH_INTENSITY:
+ case V4L2_CID_INDICATOR_INTENSITY:
+ if (ci->flash)
+ ret = v4l2_subdev_call(ci->flash,
+ core, s_ctrl,
+ &ctrl);
+ break;
+ case V4L2_CID_ZOOM_ABSOLUTE:
+ ret = mfld_isp_digital_zoom(ci, 1,
+ &ctrl.value);
+ /* add digital zoom code here */
+ break;
+ default:
+ ret = -1;
+ }
+
+ if (ret) {
+ c->error_idx = i;
+ break;
+ }
+ c->controls[i].value = ctrl.value;
+ }
+ return ret;
+}
+
+static int mfld_isp_s_ext_ctrls(struct file *file, void *fh,
+ struct v4l2_ext_controls *c)
+{
+ struct v4l2_control ctrl;
+ int i;
+ int ret = 0;
+
+ if (c->ctrl_class == V4L2_CTRL_CLASS_USER) {
+ for (i = 0; i < c->count; i++) {
+ ctrl.id = c->controls[i].id;
+ ctrl.value = c->controls[i].value;
+ ret = mfld_isp_s_ctrl(file, fh, &ctrl);
+ c->controls[i].value = ctrl.value;
+ if (ret) {
+ c->error_idx = i;
+ break;
+ }
+ }
+ return ret;
+ }
+
+ if (c->ctrl_class == V4L2_CTRL_CLASS_CAMERA)
+ return mfld_isp_camera_s_ext_ctrls(file, fh, c);
+
+ return -EINVAL;
+}
+
+static int mfld_isp_g_parm(struct file *file, void *fh,
+ struct v4l2_streamparm *parm)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_g_parm\n");
+
+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupport v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ parm->parm.capture.capturemode = ci->run_mode;
+
+ return 0;
+}
+
+static int mfld_isp_s_parm(struct file *file, void *fh,
+ struct v4l2_streamparm *parm)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret = 0;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_s_parm\n");
+
+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+ mfld_isp_dbg(KERN_ERR, "unsupport v4l2 buf type\n");
+ return -EINVAL;
+ }
+
+ ci->run_mode = parm->parm.capture.capturemode;
+ mfld_isp_dbg(KERN_DEBUG, "Set ISP running mode to %d\n", ci->run_mode);
+
+ return ret;
+}
+
+static long mfld_isp_vidioc_default(struct file *file, void *fh,
+ int cmd, void *arg)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ switch (cmd) {
+ case ATOMISP_IOC_G_XNR:
+ return mfld_isp_xnr(ci, 0, arg);
+
+ case ATOMISP_IOC_S_XNR:
+ return mfld_isp_xnr(ci, 1, arg);
+
+ case ATOMISP_IOC_G_BAYER_NR:
+ return mfld_isp_bayer_nr(ci, 0,
+ (struct sh_css_isp_nr_config *)arg);
+
+ case ATOMISP_IOC_S_BAYER_NR:
+ return mfld_isp_bayer_nr(ci, 1,
+ (struct sh_css_isp_nr_config *)arg);
+
+ case ATOMISP_IOC_G_TNR:
+ return mfld_isp_tnr(ci, 0, (struct sh_css_isp_tnr_config *)arg);
+
+ case ATOMISP_IOC_S_TNR:
+ return mfld_isp_tnr(ci, 1, (struct sh_css_isp_tnr_config *)arg);
+
+ case ATOMISP_IOC_G_HISTOGRAM:
+ return mfld_isp_histogram(ci, 0, arg);
+
+ case ATOMISP_IOC_S_HISTOGRAM:
+ return mfld_isp_histogram(ci, 1, arg);
+
+ case ATOMISP_IOC_G_BLACK_LEVEL_COMP:
+ return mfld_isp_black_level(ci, 0,
+ (struct sh_css_isp_ob_config *)arg);
+
+ case ATOMISP_IOC_S_BLACK_LEVEL_COMP:
+ return mfld_isp_black_level(ci, 1,
+ (struct sh_css_isp_ob_config *)arg);
+
+ case ATOMISP_IOC_G_YCC_NR:
+ return mfld_isp_ycc_nr(ci, 0,
+ (struct sh_css_isp_nr_config *)arg);
+
+ case ATOMISP_IOC_S_YCC_NR:
+ return mfld_isp_ycc_nr(ci, 1,
+ (struct sh_css_isp_nr_config *)arg);
+
+ case ATOMISP_IOC_G_EE:
+ return mfld_isp_ee(ci, 0, (struct sh_css_isp_ee_config *)arg);
+
+ case ATOMISP_IOC_S_EE:
+ return mfld_isp_ee(ci, 1, (struct sh_css_isp_ee_config *)arg);
+
+ case ATOMISP_IOC_G_DIS_STAT:
+ return mfld_isp_dis_stat(ci, 0,
+ (struct mfld_isp_dis_config *)arg);
+
+ case ATOMISP_IOC_S_DIS_STAT:
+ return mfld_isp_dis_stat(ci, 1,
+ (struct mfld_isp_dis_config *)arg);
+
+ case ATOMISP_IOC_G_ISP_PARM:
+ return mfld_isp_param(ci, 0, (struct mfld_isp_parm *)arg);
+
+ case ATOMISP_IOC_S_ISP_PARM:
+ return mfld_isp_param(ci, 1, (struct mfld_isp_parm *)arg);
+
+ case ATOMISP_IOC_G_3A_STAT:
+ return mfld_isp_3a_stat(ci, 0, (struct mfld_3a_stat *)arg);
+
+ case ATOMISP_IOC_G_ISP_GAMMA:
+ return mfld_isp_get_gamma(ci, 0,
+ (struct mfld_isp_gamma_tbl *)arg);
+
+ case ATOMISP_IOC_S_ISP_GAMMA:
+ return mfld_isp_set_gamma(ci, 0,
+ (struct mfld_isp_gamma_tbl *)arg);
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ci_buf_setup(struct videobuf_queue *vq,
+ unsigned int *count,
+ unsigned int *size)
+{
+ struct ci_device *ci = vq->priv_data;
+
+ if (*count == 0)
+ *count = CI_MAX_BUF_NUM;
+ else if (*count > CI_MAX_BUF_NUM)
+ *count = CI_MAX_BUF_NUM;
+
+ *size = ci->cap_fmt->imagesize;
+
+ return 0;
+}
+
+static int ci_buf_prepare(struct videobuf_queue *vq,
+ struct videobuf_buffer *vb,
+ enum v4l2_field field)
+{
+ struct ci_device *ci = vq->priv_data;
+
+ mfld_isp_dbg(KERN_DEBUG, "buf_prepare()\n");
+
+ vb->size = ci->width * ci->height * 2;
+ vb->width = ci->width;
+ vb->height = ci->height;
+ vb->field = field;
+ vb->state = VIDEOBUF_PREPARED;
+
+ return 0;
+}
+
+static void ci_buf_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
+{
+ struct ci_device *ci = vq->priv_data;
+
+ mfld_isp_dbg(KERN_DEBUG, "%s\n", __func__);
+
+ list_add_tail(&vb->queue, &ci->activeq);
+ vb->state = VIDEOBUF_QUEUED;
+}
+
+static void ci_buf_release(struct videobuf_queue *vq,
+ struct videobuf_buffer *vb)
+{
+ struct videobuf_vmalloc_memory *vm_mem = vb->priv;
+ if (vm_mem && vm_mem->vmalloc) {
+ mfld_isp_dbg(KERN_DEBUG, "%p %p\n\n", vm_mem, vm_mem->vmalloc);
+ sh_css_frame_free(vm_mem->vmalloc);
+ vm_mem->vmalloc = NULL;
+ }
+ vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static struct videobuf_queue_ops ci_video_qops = {
+ .buf_setup = ci_buf_setup,
+ .buf_prepare = ci_buf_prepare,
+ .buf_queue = ci_buf_queue,
+ .buf_release = ci_buf_release,
+};
+
+static int mfld_isp_init_struct(struct ci_device *ci)
+{
+ if (ci == NULL)
+ return -EINVAL;
+
+ ci->width = ci->height = 0;
+
+ /* init videobuf */
+ videobuf_queue_vmalloc_init(&ci->capq, &ci_video_qops, NULL,
+ &ci->irqlock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
+ V4L2_FIELD_NONE, sizeof(struct ci_buffer),
+ ci);
+ /* init locks */
+ spin_lock_init(&ci->irqlock);
+ mutex_init(&ci->mutex);
+ INIT_LIST_HEAD(&ci->activeq);
+ ci->cap_fmt = kzalloc(sizeof(struct ci_fmt), GFP_KERNEL);
+
+ ci->sh_pixelformat = -1;
+ ci->run_mode = CI_MODE_STILL_CAPTURE;
+ ci->color_effect = V4L2_COLORFX_NONE;
+ ci->bad_pixel_en = 1;
+ ci->gdc_cac_en = 0;
+ ci->video_dis_en = 0;
+ ci->sc_en = 0;
+ ci->fpn_en = 0;
+ ci->xnr_en = 0;
+ ci->false_color = 0;
+ ci->online_process = 1; /* By default we turn on online process */
+ ci->bayer_downscaling = 0; /* By default we turn on online process */
+
+ /* Add for channel */
+ if (ci->cameras[0].camera)
+ ci->camera_curr = 0;
+
+ /* TNR configure init */
+ sh_css_params_get_default_tnr_config
+ ((const struct sh_css_isp_tnr_config **)(&ci->tnr_config));
+ /* NR configure init */
+ sh_css_params_get_default_nr_config
+ ((const struct sh_css_isp_nr_config **)(&ci->nr_config));
+ /* EE configure init */
+ sh_css_params_get_default_ee_config
+ ((const struct sh_css_isp_ee_config **)(&ci->ee_config));
+ /* OB configure init */
+ sh_css_params_get_default_ob_config
+ ((const struct sh_css_isp_ob_config **)(&ci->ob_config));
+
+ return 0;
+}
+
+#ifdef USE_DYNAMIC_BIN
+char *_hrt_blob_sp;
+char *_hrt_blob_isp_bayer_ds_var;
+char *_hrt_blob_isp_copy_var;
+char *_hrt_blob_isp_primary_16mp;
+char *_hrt_blob_isp_primary_14mp;
+char *_hrt_blob_isp_primary_var;
+char *_hrt_blob_isp_primary_ds;
+char *_hrt_blob_isp_primary_small;
+char *_hrt_blob_isp_preview_var;
+char *_hrt_blob_isp_preview_ds;
+char *_hrt_blob_isp_video_online;
+char *_hrt_blob_isp_video_online_nodz;
+char *_hrt_blob_isp_video_online_ds;
+char *_hrt_blob_isp_video_offline;
+char *_hrt_blob_isp_xnr_var;
+char *_hrt_blob_isp_pregdc_var;
+char *_hrt_blob_isp_gdc_var;
+char *_hrt_blob_isp_postgdc_var;
+char *_hrt_blob_isp_vf_pp;
+
+unsigned int _hrt_text_size_of_sp;
+unsigned int _hrt_size_of_sp;
+
+unsigned int _hrt_text_size_of_isp_bayer_ds_var;
+unsigned int _hrt_size_of_isp_bayer_ds_var;
+
+unsigned int _hrt_text_size_of_isp_copy_var;
+unsigned int _hrt_size_of_isp_copy_var;
+
+unsigned int _hrt_text_size_of_isp_gdc_var;
+unsigned int _hrt_size_of_isp_gdc_var;
+
+unsigned int _hrt_text_size_of_isp_postgdc_var;
+unsigned int _hrt_size_of_isp_postgdc_var;
+
+unsigned int _hrt_text_size_of_isp_pregdc_var;
+unsigned int _hrt_size_of_isp_pregdc_var;
+
+unsigned int _hrt_text_size_of_isp_preview_ds;
+unsigned int _hrt_size_of_isp_preview_ds;
+
+unsigned int _hrt_text_size_of_isp_preview_var;
+unsigned int _hrt_size_of_isp_preview_var;
+
+unsigned int _hrt_text_size_of_isp_primary_14mp;
+unsigned int _hrt_size_of_isp_primary_14mp;
+
+unsigned int _hrt_text_size_of_isp_primary_16mp;
+unsigned int _hrt_size_of_isp_primary_16mp;
+
+unsigned int _hrt_text_size_of_isp_primary_ds;
+unsigned int _hrt_size_of_isp_primary_ds;
+
+unsigned int _hrt_text_size_of_isp_primary_small;
+unsigned int _hrt_size_of_isp_primary_small;
+
+unsigned int _hrt_text_size_of_isp_primary_var;
+unsigned int _hrt_size_of_isp_primary_var;
+
+unsigned int _hrt_text_size_of_isp_vf_pp;
+unsigned int _hrt_size_of_isp_vf_pp;
+
+unsigned int _hrt_text_size_of_isp_video_offline;
+unsigned int _hrt_size_of_isp_video_offline;
+
+unsigned int _hrt_text_size_of_isp_video_online_ds;
+unsigned int _hrt_size_of_isp_video_online_ds;
+
+unsigned int _hrt_text_size_of_isp_video_online_nodz;
+unsigned int _hrt_size_of_isp_video_online_nodz;
+
+unsigned int _hrt_text_size_of_isp_video_online;
+unsigned int _hrt_size_of_isp_video_online;
+
+unsigned int _hrt_text_size_of_isp_xnr_var;
+unsigned int _hrt_size_of_isp_xnr_var;
+
+const struct firmware *isp_fw_loaded;
+struct bi_h *isp_fw[SUPPORTED_BIN];
+
+/*
+ * Setup the blob firmware to the loaded firmware
+ * replace the file such as isp_copy_5mp.blob.h
+ * Fixme: use micro to reduce the code lines
+ */
+
+/*Load the Binary Header*/
+static void mfld_isp_get_binary_header(const struct firmware *ci_fw)
+{
+ struct bi_h *bi;
+ struct bi_file_h bf;
+ int i, binary_nr = 0;
+
+ /*bf = (struct bi_file_h *)(ci_fw->data);*/
+ memcpy(&bf, ci_fw->data, sizeof(struct bi_file_h));
+ mfld_isp_dbg(KERN_INFO, "isp fw version %d\n", bf.version);
+ binary_nr = bf.binary_nr;
+ mfld_isp_dbg(KERN_DEBUG, "Binary find %d\n", binary_nr);
+ for (i = 0; i < binary_nr + 1; i++) {
+ bi = (struct bi_h *)(ci_fw->data + sizeof(struct bi_file_h) +
+ sizeof(struct bi_h) * i);
+ mfld_isp_dbg(KERN_DEBUG, "Collect binary %d\n", i);
+ if ((bi->ID) >= 0) {
+ mfld_isp_dbg(KERN_DEBUG, "Collect correct binary %d,"
+ "binary %d\n", i, bi->ID);
+ mfld_isp_dbg(KERN_DEBUG, "Size %x, offset %x\n",
+ bi->size, bi->offset);
+ isp_fw[bi->ID] = bi;
+ }
+ }
+}
+
+static void mfld_isp_setup_fw_size(void)
+{
+ /* This is for SP binary */
+ _hrt_text_size_of_sp = isp_fw[isp_bin_sp]->text_size;
+ _hrt_size_of_sp = isp_fw[isp_bin_sp]->size;
+
+ /* This is for ISP binary */
+ _hrt_text_size_of_isp_bayer_ds_var =
+ isp_fw[isp_bin_bayer_ds_var]->text_size;
+ _hrt_size_of_isp_bayer_ds_var = isp_fw[isp_bin_bayer_ds_var]->size;
+ _hrt_text_size_of_isp_copy_var = isp_fw[isp_bin_copy_var]->text_size;
+ _hrt_size_of_isp_copy_var = isp_fw[isp_bin_copy_var]->size;
+ _hrt_text_size_of_isp_gdc_var = isp_fw[isp_bin_gdc_var]->text_size;
+ _hrt_size_of_isp_gdc_var = isp_fw[isp_bin_gdc_var]->size;
+ _hrt_text_size_of_isp_postgdc_var =
+ isp_fw[isp_bin_postgdc_var]->text_size;
+ _hrt_size_of_isp_postgdc_var = isp_fw[isp_bin_postgdc_var]->size;
+ _hrt_text_size_of_isp_pregdc_var =
+ isp_fw[isp_bin_pregdc_var]->text_size;
+ _hrt_size_of_isp_pregdc_var = isp_fw[isp_bin_pregdc_var]->size;
+ _hrt_text_size_of_isp_preview_ds =
+ isp_fw[isp_bin_preview_ds]->text_size;
+ _hrt_size_of_isp_preview_ds = isp_fw[isp_bin_preview_ds]->size;
+ _hrt_text_size_of_isp_preview_var =
+ isp_fw[isp_bin_preview_var]->text_size;
+ _hrt_size_of_isp_preview_var = isp_fw[isp_bin_preview_var]->size;
+ _hrt_text_size_of_isp_primary_14mp =
+ isp_fw[isp_bin_primary_14mp]->text_size;
+ _hrt_size_of_isp_primary_14mp = isp_fw[isp_bin_primary_14mp]->size;
+ _hrt_text_size_of_isp_primary_16mp =
+ isp_fw[isp_bin_primary_16mp]->text_size;
+ _hrt_size_of_isp_primary_16mp = isp_fw[isp_bin_primary_16mp]->size;
+ _hrt_text_size_of_isp_primary_ds =
+ isp_fw[isp_bin_primary_ds]->text_size;
+ _hrt_size_of_isp_primary_ds = isp_fw[isp_bin_primary_ds]->size;
+ _hrt_text_size_of_isp_primary_small =
+ isp_fw[isp_bin_primary_small]->text_size;
+ _hrt_size_of_isp_primary_small = isp_fw[isp_bin_primary_small]->size;
+ _hrt_text_size_of_isp_primary_var =
+ isp_fw[isp_bin_primary_var]->text_size;
+ _hrt_size_of_isp_primary_var = isp_fw[isp_bin_primary_var]->size;
+ _hrt_text_size_of_isp_vf_pp = isp_fw[isp_bin_vf_pp]->text_size;
+ _hrt_size_of_isp_vf_pp = isp_fw[isp_bin_vf_pp]->size;
+ _hrt_text_size_of_isp_video_offline =
+ isp_fw[isp_bin_video_offline]->text_size;
+ _hrt_size_of_isp_video_offline = isp_fw[isp_bin_video_offline]->size;
+ _hrt_text_size_of_isp_video_online_ds =
+ isp_fw[isp_bin_video_online_ds]->text_size;
+ _hrt_size_of_isp_video_online_ds =
+ isp_fw[isp_bin_video_online_ds]->size;
+ _hrt_text_size_of_isp_video_online_nodz =
+ isp_fw[isp_bin_video_online_nodz]->text_size;
+ _hrt_size_of_isp_video_online_nodz =
+ isp_fw[isp_bin_video_online_nodz]->size;
+ _hrt_text_size_of_isp_video_online =
+ isp_fw[isp_bin_video_online]->text_size;
+ _hrt_size_of_isp_video_online = isp_fw[isp_bin_video_online]->size;
+ _hrt_text_size_of_isp_xnr_var = isp_fw[isp_bin_xnr_var]->text_size;
+ _hrt_size_of_isp_xnr_var = isp_fw[isp_bin_xnr_var]->size;
+}
+
+static void mfld_isp_setup_fw(const struct firmware *ci_fw)
+{
+ _hrt_blob_sp = (char *)
+ (isp_fw[isp_bin_sp]->offset + ci_fw->data);
+
+ _hrt_blob_isp_copy_var = (char *)
+ (isp_fw[isp_bin_copy_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_bayer_ds_var = (char *)
+ (isp_fw[isp_bin_bayer_ds_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_primary_16mp = (char *)
+ (isp_fw[isp_bin_primary_16mp]->offset + ci_fw->data);
+
+ _hrt_blob_isp_primary_14mp = (char *)
+ (isp_fw[isp_bin_primary_14mp]->offset + ci_fw->data);
+
+ _hrt_blob_isp_primary_var = (char *)
+ (isp_fw[isp_bin_primary_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_primary_ds = (char *)
+ (isp_fw[isp_bin_primary_ds]->offset + ci_fw->data);
+
+ _hrt_blob_isp_primary_small = (char *)
+ (isp_fw[isp_bin_primary_small]->offset + ci_fw->data);
+
+ _hrt_blob_isp_preview_var = (char *)
+ (isp_fw[isp_bin_preview_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_preview_ds = (char *)
+ (isp_fw[isp_bin_preview_ds]->offset + ci_fw->data);
+
+ _hrt_blob_isp_video_online = (char *)
+ (isp_fw[isp_bin_video_online]->offset + ci_fw->data);
+
+ _hrt_blob_isp_video_online_ds = (char *)
+ (isp_fw[isp_bin_video_online_ds]->offset + ci_fw->data);
+
+ _hrt_blob_isp_video_online_nodz = (char *)
+ (isp_fw[isp_bin_video_online_nodz]->offset + ci_fw->data);
+
+ _hrt_blob_isp_video_offline = (char *)
+ (isp_fw[isp_bin_video_offline]->offset + ci_fw->data);
+
+ _hrt_blob_isp_pregdc_var = (char *)
+ (isp_fw[isp_bin_pregdc_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_gdc_var = (char *)
+ (isp_fw[isp_bin_gdc_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_postgdc_var = (char *)
+ (isp_fw[isp_bin_postgdc_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_xnr_var = (char *)
+ (isp_fw[isp_bin_xnr_var]->offset + ci_fw->data);
+
+ _hrt_blob_isp_vf_pp = (char *)
+ (isp_fw[isp_bin_vf_pp]->offset + ci_fw->data);
+
+ mfld_isp_setup_fw_size();
+}
+
+/*
+ * Load the firmware from the User with the udev help
+ * Todo: Do we need to save the loaded firmware to some where else?
+ */
+/*static struct platform_device *ci_pdev;*/
+static int mfld_isp_load_all_firmwares(struct device *dev)
+{
+ int rc = 0;
+ mfld_isp_dbg(KERN_INFO, "loading isp firmware ...\n");
+
+ rc = request_firmware(&isp_fw_loaded, FW_PATH, dev);
+ if (rc < 0) {
+ if (rc == -ENOENT)
+ mfld_isp_dbg(KERN_INFO,
+ "atomisp: Error firmware %s not found.\n",
+ FW_PATH);
+ else
+ mfld_isp_dbg(KERN_INFO,
+ "atomisp: Error %d while requesting"
+ " firmware %s\n", rc, FW_PATH);
+ /*platform_device_unregister(ci_pdev);*/
+ return rc;
+ }
+ mfld_isp_dbg(KERN_DEBUG,
+ "isp_fw_file info: file:%p, size:%x\n",
+ isp_fw_loaded->data,
+ isp_fw_loaded->size);
+ mfld_isp_get_binary_header(isp_fw_loaded);
+ mfld_isp_setup_fw(isp_fw_loaded);
+ /*mfld_isp_setup_parm(isp_fw_loaded);*/
+ mfld_isp_dbg(KERN_INFO, "loading isp firmware ... done\n");
+ return rc;
+}
+
+static void mfld_isp_release_firmware(void)
+{
+ if (isp_fw_loaded != NULL) {
+ release_firmware(isp_fw_loaded);
+ isp_fw_loaded = NULL;
+ }
+}
+#endif
+
+static void *kernel_malloc(size_t bytes)
+{
+ return kmalloc(bytes, GFP_KERNEL);
+}
+
+/* kfree is declared with const void * argument even though it's
+ clearly not const. We work around this here. */
+static void kernel_free(void *ptr)
+{
+ kfree(ptr);
+}
+
+int myprintk(const char *fmt, ...)
+{
+ va_list args;
+ int printed;
+
+ va_start(args, fmt);
+ printed = vprintk(fmt, args);
+ va_end(args);
+
+ return printed;
+}
+
+/*
+ * file operation functions
+ */
+static int mfld_isp_open(struct file *file)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_open\n");
+ if (isp_probe == 0)
+ return -1;
+
+ if (ci->open) {
+ mfld_isp_dbg(KERN_ERR, "Can only open once now\n");
+ return -EBUSY;
+ }
+
+ /* runtime power management, turn on ISP */
+ ret = pm_runtime_get_sync(vdev->v4l2_dev->dev);
+ if (ret < 0) {
+ mfld_isp_dbg(KERN_ERR, "Failed to power on device\n");
+ return -EINVAL;
+ }
+
+ ci->open++;
+
+ ret = mfld_isp_init_struct(ci);
+ if (ret)
+ return ret;
+
+
+#ifdef USE_DYNAMIC_BIN
+ /* Load firmware from user space */
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ core, init, 1);
+
+ if (ret == -1 || ret == -EINVAL) {
+ mfld_isp_dbg(KERN_ERR, "sensor firmware failed\n");
+ return ret;
+ }
+
+ if (mfld_isp_load_all_firmwares(&vdev->dev) < 0) {
+ mfld_isp_dbg(KERN_ERR, "Load firmwares failed\n");
+ ci->open--;
+ pm_runtime_put(vdev->v4l2_dev->dev);
+ return -1;
+ }
+#endif
+ /* Init ISP */
+ return_on_css_error(sh_css_init
+ (kernel_malloc, kernel_free,
+ sh_css_interrupt_setting_disabled));
+ return_on_css_error(sh_css_set_print_function(myprintk));
+
+ return_on_css_error(sh_css_params_allocate(&ci->isp_params));
+ /* now set the default parameters. */
+ return_on_css_error(sh_css_params_default(ci->isp_params));
+
+ mfld_isp_dbg(KERN_DEBUG, "open done\n");
+
+ return 0;
+}
+
+static int mfld_isp_close(struct ci_device *ci)
+{
+ int ret;
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_close\n");
+
+ if (ci == NULL)
+ return -EBADF;
+
+ if (ci->open <= 0) {
+ mfld_isp_dbg(KERN_ALERT, "device already closed\n");
+ return -EBADF;
+ }
+ /* in case image buf is not freed */
+ if (ci->capq.bufs[0]) {
+ mutex_lock(&ci->capq.vb_lock);
+ videobuf_queue_cancel(&ci->capq);
+ mutex_unlock(&ci->capq.vb_lock);
+ }
+ kfree(ci->cap_fmt);
+
+#ifdef USE_DYNAMIC_BIN
+ mfld_isp_release_firmware();
+#endif
+
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera,
+ core, init, 0);
+
+ if (ret == -1 || ret == -EINVAL) {
+ mfld_isp_dbg(KERN_ERR, "sensor firmware failed\n");
+ return ret;
+ }
+
+ ci->open--;
+
+ sh_css_uninit();
+
+ /* uninit ISP parameter */
+ sh_css_params_free(ci->isp_params);
+ return 0;
+}
+
+static int mfld_isp_release(struct file *file)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_release\n");
+
+ ret = mfld_isp_close(ci);
+ if (!ret)
+ pm_runtime_put(vdev->v4l2_dev->dev);
+
+ return ret;
+}
+
+static int __do_isp_mm_remap(struct vm_area_struct *vma,
+ void *isp_virt, __u32 host_virt, __u32 pgnr)
+{
+ __u32 pfn;
+
+ while (pgnr) {
+ pfn = hmm_virt_to_phys(isp_virt) >> PAGE_SHIFT;
+ if (remap_pfn_range(vma, host_virt, pfn,
+ PAGE_SIZE, PAGE_SHARED)) {
+ mfld_isp_dbg(KERN_ERR, "remap_pfn_range err.\n");
+ return -1;
+ }
+
+ isp_virt += PAGE_SIZE;
+ host_virt += PAGE_SIZE;
+ pgnr--;
+ }
+
+ return 0;
+}
+
+static int frame_mmap(const struct sh_css_frame *frame,
+ struct vm_area_struct *vma)
+{
+ void *isp_virt;
+ __u32 host_virt;
+ __u32 pgnr;
+
+ if (!frame) {
+ mfld_isp_dbg(KERN_ERR, "NULL frame pointer.\n");
+ return -EINVAL;
+ }
+
+ host_virt = vma->vm_start;
+ isp_virt = frame->data;
+ get_frame_pgnr(frame, &pgnr);
+
+ if (__do_isp_mm_remap(vma, isp_virt, host_virt, pgnr))
+ return -1;
+
+ return 0;
+}
+
+static int mfld_videobuf_mmap_mapper(struct videobuf_queue *q,
+ struct vm_area_struct *vma)
+{
+ __u32 offset = vma->vm_pgoff << PAGE_SHIFT;
+ int ret = -EINVAL, i;
+ struct videobuf_vmalloc_memory *vm_mem;
+ struct videobuf_mapping *map;
+
+ MAGIC_CHECK(q->int_ops->magic, MAGIC_QTYPE_OPS);
+ if (!(vma->vm_flags & VM_WRITE) || !(vma->vm_flags & VM_SHARED)) {
+ mfld_isp_dbg(KERN_ERR, "map appl bug:"
+ " PROT_WRITE and MAP_SHARED are required\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&q->vb_lock);
+ for (i = 0; i < MIN(VIDEO_MAX_FRAME, CI_MAX_BUF_NUM); i++) {
+ struct videobuf_buffer *buf = q->bufs[i];
+ map = kzalloc(sizeof(struct videobuf_mapping), GFP_KERNEL);
+
+ buf->map = map;
+ map->start = vma->vm_start;
+ map->end = vma->vm_end;
+ map->q = q;
+
+ buf->baddr = vma->vm_start;
+
+ if (buf && buf->memory == V4L2_MEMORY_MMAP &&
+ buf->boff == offset) {
+ vm_mem = buf->priv;
+ mfld_isp_dbg(KERN_DEBUG, "mmap %p\n", vm_mem->vmalloc);
+ ret = frame_mmap(vm_mem->vmalloc, vma);
+ break;
+ }
+
+ vma->vm_flags |= VM_DONTEXPAND | VM_RESERVED;
+ }
+ mutex_unlock(&q->vb_lock);
+
+ return ret;
+}
+
+static int mfld_isp_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ __u32 start = vma->vm_start;
+ __u32 end = vma->vm_end;
+ __u32 size = end - start;
+ __u32 origin_size, new_size;
+ struct sh_css_frame *raw_virt_addr;
+
+ mfld_isp_dbg(KERN_DEBUG, "mfld_isp_mmap\n");
+
+ if (!(vma->vm_flags & (VM_WRITE | VM_READ)))
+ return -EACCES;
+
+ if (!(vma->vm_flags & VM_SHARED))
+ return -EINVAL;
+
+ new_size = ci->width * ci->height * 2;
+
+ /*
+ * mmap for ISP parameter structure
+ */
+ if (vma->vm_pgoff == (ISP_PARAM_MMAP_OFFSET >> PAGE_SHIFT)) {
+ if (ci->online_process != 0)
+ return -EINVAL;
+
+ raw_virt_addr = sh_css_get_raw_frame();
+ if (raw_virt_addr == NULL) {
+ mfld_isp_dbg(KERN_ERR, "Failed to request RAW frame\n");
+ return -EINVAL;
+ }
+ sh_css_remove_pad_from_frame(raw_virt_addr,
+ W_PAD, ci->width, ci->height);
+ origin_size = raw_virt_addr->data_bytes;
+ raw_virt_addr->data_bytes = new_size;
+
+ mfld_isp_dbg(KERN_DEBUG, "raw = %x, size = %d, ALIGN = %d\n",
+ (unsigned int)raw_virt_addr, size,
+ PAGE_ALIGN(raw_virt_addr->data_bytes));
+ if (size != PAGE_ALIGN(new_size)) {
+ mfld_isp_dbg(KERN_ERR, "incorrect size for mmap ISP"
+ " Raw Frame\n");
+ return -EINVAL;
+ }
+
+ /*ci->online_process = 0;*/
+ /*return_on_css_error(sh_css_capture_enable_online*/
+ /*(ci->online_process));*/
+ if (frame_mmap(raw_virt_addr, vma)) {
+ mfld_isp_dbg(KERN_ERR, "frame_mmap failed.\n");
+ raw_virt_addr->data_bytes = origin_size;
+ return -1;
+ }
+ raw_virt_addr->data_bytes = origin_size;
+ vma->vm_flags |= VM_RESERVED;
+ return 0;
+ }
+
+ /*
+ * mmap for NORMAL frames
+ */
+
+ return mfld_videobuf_mmap_mapper(&ci->capq, vma);
+}
+
+static unsigned int mfld_isp_poll(struct file *file,
+ struct poll_table_struct *pt)
+{
+ struct video_device *vdev = video_devdata(file);
+ struct ci_device *ci = video_get_drvdata(vdev);
+
+ if (ci->capq.streaming != 1)
+ return POLLERR;
+
+ return POLLIN | POLLRDNORM;
+}
+
+static const struct v4l2_file_operations mfld_isp_fops = {
+ .owner = THIS_MODULE,
+ .open = mfld_isp_open,
+ .release = mfld_isp_release,
+ .mmap = mfld_isp_mmap,
+ .ioctl = video_ioctl2,
+ .poll = mfld_isp_poll,
+};
+
+static const struct v4l2_ioctl_ops mfld_isp_ioctl_ops = {
+ .vidioc_querycap = mfld_isp_querycap,
+ .vidioc_g_chip_ident = mfld_isp_g_chip_ident,
+ .vidioc_enum_input = mfld_isp_enum_input,
+ .vidioc_g_input = mfld_isp_g_input,
+ .vidioc_s_input = mfld_isp_s_input,
+ .vidioc_queryctrl = mfld_isp_queryctl,
+ .vidioc_s_ctrl = mfld_isp_s_ctrl,
+ .vidioc_g_ctrl = mfld_isp_g_ctrl,
+ .vidioc_s_ext_ctrls = mfld_isp_s_ext_ctrls,
+ .vidioc_g_ext_ctrls = mfld_isp_g_ext_ctrls,
+ .vidioc_enum_fmt_vid_cap = mfld_isp_enum_fmt_cap,
+ .vidioc_try_fmt_vid_cap = mfld_isp_try_fmt_cap,
+ .vidioc_g_fmt_vid_cap = mfld_isp_g_fmt_cap,
+ .vidioc_s_fmt_vid_cap = mfld_isp_s_fmt_cap,
+ .vidioc_s_fmt_type_private = mfld_isp_s_fmt_cap,
+ .vidioc_reqbufs = mfld_isp_reqbufs,
+ .vidioc_querybuf = mfld_isp_querybuf,
+ .vidioc_qbuf = mfld_isp_qbuf,
+ .vidioc_dqbuf = mfld_isp_dqbuf,
+ .vidioc_streamon = mfld_isp_streamon,
+ .vidioc_streamoff = mfld_isp_streamoff,
+ .vidioc_default = mfld_isp_vidioc_default,
+ .vidioc_cropcap = mfld_isp_cropcap,
+ .vidioc_enum_framesizes = mfld_isp_enum_framesizes,
+ .vidioc_enum_frameintervals = mfld_isp_enum_frameintervals,
+ .vidioc_s_parm = mfld_isp_s_parm,
+ .vidioc_g_parm = mfld_isp_g_parm,
+ .vidioc_g_std = mfld_isp_g_std,
+ .vidioc_s_std = mfld_isp_s_std,
+ .vidioc_g_crop = mfld_isp_g_crop,
+ .vidioc_s_crop = mfld_isp_s_crop,
+};
+
+static const struct video_device mfld_isp_video_dev = {
+ .name = "mfld_ci",
+ .minor = -1,
+ .fops = &mfld_isp_fops,
+ .release = video_device_release,
+ .ioctl_ops = &mfld_isp_ioctl_ops
+};
+
+#ifdef CONFIG_PM
+static int ospm_power_island_down(struct ci_device *);
+static int ospm_power_island_up(struct ci_device *);
+
+static int mfld_isp_runtime_suspend(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct ci_device *ci = (struct ci_device *)pci_get_drvdata(pdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "Get into runtime suspend function\n");
+
+ ret = pci_save_state(pdev);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "pci_save_state failed %d\n", ret);
+ return ret;
+ }
+
+ pci_disable_device(pdev);
+ ret += pci_set_power_state(pdev, PCI_D3hot);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "fail to set power state\n");
+ return ret;
+ }
+
+ ospm_power_island_down(ci);
+
+ mfld_isp_dbg(KERN_DEBUG, "Leave runtime suspend function\n");
+ return 0;
+}
+
+static int mfld_isp_runtime_resume(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct ci_device *ci = (struct ci_device *)pci_get_drvdata(pdev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "Get into runtime resume function\n");
+
+ pci_set_power_state(pdev, PCI_D0);
+ ospm_power_island_up(ci);
+ pci_restore_state(pdev);
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "fail to enable device in resume\n");
+ return ret;
+ }
+
+ mfld_isp_dbg(KERN_DEBUG, "Leave runtime resume function\n");
+ return 0;
+}
+
+static int mfld_isp_pci_suspend(struct pci_dev *dev, pm_message_t state)
+{
+ struct ci_device *ci = (struct ci_device *)pci_get_drvdata(dev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "Get into suspend function\n");
+
+#if (!defined(IMAGE_FROM_TPG))
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera, core,
+ s_power, 0);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "Fail to suspend sensor\n");
+ return ret;
+ }
+#endif
+
+ ret = pci_save_state(dev);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "pci_save_state failed %d\n", ret);
+ return ret;
+ }
+
+ pci_disable_device(dev);
+ ret += pci_set_power_state(dev, pci_choose_state(dev, state));
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "fail to set power state\n");
+ return ret;
+ }
+
+ ospm_power_island_down(ci);
+
+ mfld_isp_dbg(KERN_DEBUG, "Leave suspend function\n");
+ return 0;
+}
+
+static int mfld_isp_pci_resume(struct pci_dev *dev)
+{
+ struct ci_device *ci = (struct ci_device *)pci_get_drvdata(dev);
+ int ret;
+
+ mfld_isp_dbg(KERN_DEBUG, "Get into resume function\n");
+
+ pci_set_power_state(dev, PCI_D0);
+ ospm_power_island_up(ci);
+ pci_restore_state(dev);
+
+ ret = pci_enable_device(dev);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "fail to enable device in resume\n");
+ return ret;
+ }
+#if (!defined(IMAGE_FROM_TPG))
+ ret = v4l2_subdev_call(ci->cameras[ci->camera_curr].camera, core,
+ s_power, 1);
+ if (ret) {
+ mfld_isp_dbg(KERN_ERR, "Fail to resume sensor\n");
+ return ret;
+ }
+#endif
+
+ mfld_isp_dbg(KERN_DEBUG, "Leave resume function\n");
+ return 0;
+}
+#endif
+
+#ifdef PNW_B0
+static void set_alt_fn_for_i2c4_5(void)
+{
+ void __iomem *gpio1_base;
+ u32 gafr4_l;
+
+ gpio1_base = ioremap_nocache(0xff12c800, 0x74);
+ if (!gpio1_base)
+ mfld_isp_dbg(KERN_DEBUG, "gpio1_base mapped failed\n");
+
+ mfld_isp_dbg(KERN_DEBUG, "try to set alt fn for i2c4\n");
+
+ /* GPIO O/P Enable */
+ writel(0xffe80303, gpio1_base + 0x10);
+ mfld_isp_dbg(KERN_DEBUG, "(0xffe80303)0x%x\n",
+ readl(gpio1_base + 0x10));
+ gafr4_l = readl(gpio1_base + 0x5c);
+ mfld_isp_dbg(KERN_DEBUG, "orig vale- 0x%x", gafr4_l);
+ writel((gafr4_l | 0x00055000), gpio1_base + 0x5c);
+
+ gafr4_l = readl(gpio1_base + 0x5c);
+ mfld_isp_dbg(KERN_DEBUG, "change val - 0x%x", gafr4_l);
+
+ mfld_isp_dbg(KERN_DEBUG, "done set alt fn for i2c4\n");
+
+}
+
+/*
+ * port: 0 is 4 Lane port and 1 is 1 Lane port
+ * flag: 0 is off and 1 is on
+ */
+static int mfld_isp_camera_flis_clock(int port, int flag)
+{
+ u32 *ipc_wbuf;
+ u8 cbuf[16] = { '\0' };
+ int ipc_ret = 0;
+
+ ipc_wbuf = (u32 *)&cbuf;
+ cbuf[0] = port; /* 0 - 14MP camera, 1 - 2MP camera */
+ cbuf[1] = flag; /* 0 - off, 1 - on */
+ /* is this correct for sub type */
+ ipc_ret = intel_scu_ipc_command(0xE7, 0,
+ ipc_wbuf, 2, NULL, 0);
+
+ if (ipc_ret != 0)
+ mfld_isp_dbg(KERN_CRIT, "Error Setting Camera FLIS Clock %x\n",
+ ipc_ret);
+
+ return ipc_ret;
+
+}
+#endif
+
+static int mfld_isp_subdev_probe(struct ci_device *ci_dev)
+{
+ struct v4l2_subdev *subdev = NULL;
+ struct i2c_adapter *adapter = NULL;
+ int i;
+
+ /* This Code is for Penwell B0 ES2 board only */
+ /* turn on vprog2 and vpro1 power */
+ __u16 ipc_addr = 0xd6;
+ __u8 ipc_data = 0xff;
+ intel_scu_ipc_iowrite8(ipc_addr, ipc_data);
+ mfld_isp_dbg(KERN_DEBUG, "turn on vprog2 power\n");
+
+ ipc_addr = 0xd7;
+ ipc_data = 0xff;
+ intel_scu_ipc_iowrite8(ipc_addr, ipc_data);
+ mfld_isp_dbg(KERN_DEBUG, "turn on vprog1 power\n");
+
+ /* Fixme: Add power control here for sensor */
+ for (i = 0; i < N_SUBDEV; i++) {
+ struct mfld_isp_subdev *info = &mfld_isp_subdev_table[i];
+
+ printk(KERN_INFO "name %s, addr %d, id %d\n",
+ info->board_info.type, info->board_info.addr,
+ info->i2c_adapter_id);
+
+ /* turn on camera flis register*/
+ mfld_isp_dbg(KERN_INFO, "turn on camera flis clock\n");
+ if (info->subdev_type == SECONDARY_CAMERA)
+ mfld_isp_camera_flis_clock(1, 1);
+ else
+ mfld_isp_camera_flis_clock(0, 1);
+
+ set_alt_fn_for_i2c4_5();
+
+ adapter = i2c_get_adapter(info->i2c_adapter_id);
+ if (adapter == NULL) {
+ mfld_isp_dbg(KERN_ERR,
+ "Failed to find i2c adapter for"
+ "subdev %s\n", info->board_info.type);
+ break;
+ }
+ mfld_isp_dbg(KERN_INFO, "Found adapter %s for subdev %s\n",
+ adapter->name, info->board_info.type);
+
+ subdev = v4l2_i2c_new_subdev_board(&ci_dev->v4l2_dev, adapter,
+ NULL, &info->board_info,
+ NULL, 1);
+ if (subdev == NULL) {
+ printk(KERN_WARNING "Subdev %s registration failed\n",
+ info->board_info.type);
+ continue;
+ }
+
+ mfld_isp_dbg(KERN_INFO, "Subdev %s successfully register\n",
+ info->board_info.type);
+
+ switch (info->subdev_type) {
+ case PRIMARY_CAMERA:
+ case SECONDARY_CAMERA:
+ printk(KERN_INFO "atomisp: sensor probed\n");
+ ci_dev->cameras[ci_dev->camera_cnt++].camera = subdev;
+ case CAMERA_MOTOR:
+ printk(KERN_INFO "atomisp: motor probed\n");
+ ci_dev->motor = subdev;
+ break;
+ case LED_FLASH:
+ case XENON_FLASH:
+ ci_dev->flash = subdev;
+ }
+
+ }
+
+ /*Check camera for at least one subdev in it */
+ if (!ci_dev->cameras[0].camera) {
+ printk(KERN_INFO "atomisp: "
+ "no camera attached or fail to detect\n");
+ return -ENODEV;
+ }
+ printk(KERN_INFO "atomisp: %d camera detect\n", ci_dev->camera_cnt);
+ return 0;
+}
+
+static inline u32 MSG_READ32(uint port, uint offset)
+{
+ int mcr = (0x10 << 24) | (port << 16) | (offset << 8);
+ outl(0x800000D0, 0xCF8);
+ outl(mcr, 0xCFC);
+ outl(0x800000D4, 0xCF8);
+ return inl(0xcfc);
+}
+
+static inline void MSG_WRITE32(uint port, uint offset, u32 value)
+{
+ int mcr = (0x11 << 24) | (port << 16) | (offset << 8) | 0xF0;
+ outl(0x800000D4, 0xCF8);
+ outl(value, 0xcfc);
+ outl(0x800000D0, 0xCF8);
+ outl(mcr, 0xCFC);
+}
+
+#define OSPM_ISP_D3_MASK 0x300
+#define OSPM_CAMERA_D3_MASK 0xC00
+#define OSPM_PUNIT_APM_STS 0x4
+static int ospm_power_island_down(struct ci_device *ci_dev)
+{
+ u32 pwr_cnt = 0;
+ u32 pwr_mask = 0;
+ u32 pwr_sts = 0;
+ int count = 0;
+
+ mfld_isp_dbg(KERN_INFO, "Entry %s\n", __func__);
+
+ pwr_cnt |= OSPM_ISP_D3_MASK;
+ pwr_mask |= OSPM_ISP_D3_MASK;
+
+ pwr_cnt |= inl(ci_dev->apm_base);
+ mfld_isp_dbg(KERN_INFO, "%s, set pwr_cnt = %x\n", __func__, pwr_cnt);
+ outl(pwr_cnt, ci_dev->apm_base);
+
+ pwr_cnt = inl(ci_dev->apm_base);
+ mfld_isp_dbg(KERN_INFO, "%s, get pwr_cnt = %x\n", __func__, pwr_cnt);
+ while (true) {
+ pwr_sts = inl(ci_dev->apm_base + OSPM_PUNIT_APM_STS);
+ if ((pwr_sts & pwr_mask) == pwr_mask)
+ break;
+ else {
+ mfld_isp_dbg(KERN_INFO,
+ "Checking APM_STS register pwr_sts = %x\n",
+ pwr_sts);
+ if (count++ > 500)
+ break;
+ udelay(10);
+ }
+ }
+#ifdef ISP_CTRL_DPHY
+ /* Workaround to poweroff Iunitphy when no sensor attched */
+ pwr_cnt = MSG_READ32(0x09, 0x03);
+ pwr_cnt |= 0x300;
+ MSG_WRITE32(0x09, 0x03, pwr_cnt);
+#endif
+
+ mfld_isp_dbg(KERN_INFO, "Exit %s\n", __func__);
+ return 0;
+}
+
+static int ospm_power_island_up(struct ci_device *ci_dev)
+{
+ u32 pwr_cnt = 0;
+ u32 pwr_mask = 0;
+ u32 pwr_sts = 0;
+ int count = 0;
+
+ mfld_isp_dbg(KERN_INFO, "Entry %s\n", __func__);
+
+ pwr_cnt |= inl(ci_dev->apm_base);
+
+ pwr_cnt &= ~OSPM_ISP_D3_MASK;
+ pwr_mask |= OSPM_ISP_D3_MASK;
+
+ outl(pwr_cnt, ci_dev->apm_base);
+ while (true) {
+ pwr_sts = inl(ci_dev->apm_base + OSPM_PUNIT_APM_STS);
+ if ((pwr_sts & pwr_mask) == 0)
+ break;
+ else {
+ mfld_isp_dbg(KERN_INFO, "Checking APM_STS register\n");
+ if (count++ > 500)
+ break;
+ udelay(10);
+ }
+ }
+#ifdef ISP_CTRL_DPHY
+ /* Workaround to power-on Iunitphy when no sensor attched */
+ pwr_cnt = MSG_READ32(0x09, 0x03);
+ pwr_cnt &= ~0x300;
+ MSG_WRITE32(0x09, 0x03, pwr_cnt);
+#endif
+
+ mfld_isp_dbg(KERN_INFO, "Exit %s\n", __func__);
+ return 0;
+}
+
+static int mfld_isp_ospm_init(struct ci_device *ci_dev)
+{
+ struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+
+ pci_write_config_dword(pci_root, 0xD0, 0x10047800);
+ pci_read_config_dword(pci_root, 0xD4, &ci_dev->ospm_base);
+ ci_dev->ospm_base &= 0xffff;
+ ci_dev->apm_reg = MSG_READ32(0x04, 0x7A);
+ ci_dev->apm_base = ci_dev->apm_reg & 0xffff;
+
+ mfld_isp_dbg(KERN_INFO, "OSPM_BASE = %x, APM_BASE = %x\n",
+ ci_dev->ospm_base, ci_dev->apm_base);
+ return 0;
+}
+
+static struct pci_driver mfld_isp_pci_driver;
+static int __devinit mfld_isp_pci_probe(struct pci_dev *dev,
+ const struct pci_device_id *id)
+{
+ struct ci_device *ci_dev;
+ struct video_device *vdev;
+ unsigned int start, len;
+ void __iomem *base = NULL;
+ int err;
+
+ isp_probe = 0;
+
+ ci_dev = kmalloc(sizeof(struct ci_device), GFP_KERNEL);
+ if (!dev) {
+ dev_err(&dev->dev, "Failed to alloc CI ISP structure\n");
+ err = -ENOMEM;
+ goto kmalloc_fail1;
+ }
+ memset(ci_dev, 0, sizeof(struct ci_device));
+
+ init_waitqueue_head(&ci_dev->wq_frame_complete);
+
+ err = v4l2_device_register(&dev->dev, &ci_dev->v4l2_dev);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR, "v4l2_device_register err.\n");
+ return err;
+ }
+
+ mfld_isp_dbg(KERN_INFO, "Initialising driver...\n");
+ err = pci_enable_device(dev);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR, "Failed to enable CI ISP device\n");
+ goto exit;
+ }
+
+ start = pci_resource_start(dev, 0);
+ len = pci_resource_len(dev, 0);
+
+ if (!start || len <= 0) {
+ start = 0xDF800000;
+ len = 0x400000;
+ }
+ mfld_isp_dbg(KERN_INFO, "MFLD ISP resource start 0x%x, len %d\n",
+ start, len);
+
+ err = pci_request_region(dev, 0, mfld_isp_pci_driver.name);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR, "Failed to request region 0x%1x-0x%Lx\n",
+ start, (unsigned long long)pci_resource_end(dev,
+ 0));
+ goto exit;
+ }
+
+ base = ioremap_nocache(start, len);
+ if (!base) {
+ mfld_isp_dbg(KERN_ERR, "Failed to I/O memory remapping\n");
+ err = -ENOMEM;
+ goto ioremap_fail;
+ }
+ mfld_isp_dbg(KERN_INFO, "MFLD ISP base address 0x%8x\n",
+ (unsigned int)base);
+
+ pci_set_master(dev);
+
+ vdev = video_device_alloc();
+ if (!vdev) {
+ mfld_isp_dbg(KERN_ERR, "Failed to alloc video device\n");
+ err = -ENOMEM;
+ goto alloc_vdev_fail;
+ }
+ memcpy(vdev, &mfld_isp_video_dev, sizeof(struct video_device));
+ video_set_drvdata(vdev, ci_dev);
+ vdev->debug = 0;
+ vdev->v4l2_dev = &ci_dev->v4l2_dev;
+
+ if (video_register_device(vdev, VFL_TYPE_GRABBER, -1) != 0) {
+ mfld_isp_dbg(KERN_ERR, "Failed to register video device\n");
+ err = -EINVAL;
+ goto register_fail;
+ }
+
+ snprintf(vdev->name, sizeof(vdev->name), "%s (%i)",
+ mfld_isp_video_dev.name, vdev->minor);
+
+ nr = vdev->minor;
+ mfld_isp_dbg(KERN_INFO, "Set nr to %d\n", nr);
+ ci_dev->vdev = vdev;
+ ci_dev->open = 0;
+ ci_dev->tvnorm = tvnorms;
+ ci_dev->base = base;
+ CI_DEV = ci_dev;
+ io_base = base;
+ VDEV = vdev;
+
+ /*init OSPM related varible */
+ mfld_isp_dbg(KERN_INFO, "Init OSPM for ISP\n");
+ mfld_isp_ospm_init(ci_dev);
+
+ pci_set_drvdata(dev, ci_dev);
+
+#if (!defined(IMAGE_FROM_TPG))
+ err = mfld_isp_subdev_probe(ci_dev);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR,
+ "Failed to probe camera subdev module\n");
+ goto subdev_probe_fail;
+ }
+#endif
+ err = pci_enable_msi(dev);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR,
+ "Failed to enable msi\n");
+ goto subdev_probe_fail;
+ }
+ err = request_irq(dev->irq, atomisp_isr,
+ IRQF_SHARED, "isp_irq", ci_dev);
+ if (err) {
+ mfld_isp_dbg(KERN_ERR,
+ "Failed to request irq\n");
+ pci_disable_msi(dev);
+ goto subdev_probe_fail;
+ }
+ msi_irq_init(dev);
+
+ mfld_isp_dbg(KERN_INFO, "rumtime power management init\n");
+ pm_runtime_set_active(&dev->dev);
+ pm_runtime_enable(&dev->dev);
+ /*pm_rumtime_suspend(&dev->dev); */
+
+ mfld_isp_dbg(KERN_INFO, "Initialising atom isp driver done...\n");
+ isp_probe = 1;
+
+ return 0;
+
+#if (!defined(IMAGE_FROM_TPG))
+subdev_probe_fail:
+ pci_set_drvdata(dev, NULL);
+#endif
+
+register_fail:
+ video_device_release(vdev);
+alloc_vdev_fail:
+ kfree(ci_dev);
+kmalloc_fail1:
+ iounmap(base);
+ioremap_fail:
+ pci_release_region(dev, 0);
+exit:
+ return err;
+}
+
+static void __devexit mfld_isp_pci_remove(struct pci_dev *dev)
+{
+ struct ci_device *ci_dev = (struct ci_device *)pci_get_drvdata(dev);
+ mfld_isp_dbg(KERN_INFO, "remove driver...\n");
+
+ if (ci_dev->vdev != VDEV) {
+ mfld_isp_dbg(KERN_WARNING, "VDEV has been changed\n");
+ ci_dev->vdev = VDEV;
+ }
+
+ if (ci_dev->vdev->minor != nr) {
+ mfld_isp_dbg(KERN_WARNING, "NOTE, set the minor number back"
+ "to it's real value %d\n", nr);
+ ci_dev->vdev->minor = nr;
+ }
+
+ msi_irq_uninit(dev);
+ free_irq(dev->irq, ci_dev);
+ pci_disable_msi(dev);
+
+ video_unregister_device(ci_dev->vdev);
+ video_device_release(ci_dev->vdev);
+ /* in case user forget to close */
+ if (ci_dev->open > 0)
+ mfld_isp_close(ci_dev);
+
+ pci_set_drvdata(dev, NULL);
+ iounmap(ci_dev->base);
+ kfree(ci_dev);
+ pci_release_region(dev, 0);
+}
+
+static DEFINE_PCI_DEVICE_TABLE(mfld_isp_pci_tbl) = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0148)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0149)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014A)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014B)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014C)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014D)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014E)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x014F)},
+ {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, mfld_isp_pci_tbl);
+
+static const struct dev_pm_ops mfld_isp_pm_ops = {
+ .runtime_suspend = mfld_isp_runtime_suspend,
+ .runtime_resume = mfld_isp_runtime_resume,
+};
+
+static struct pci_driver mfld_isp_pci_driver = {
+ .driver = {
+ .pm = &mfld_isp_pm_ops,
+ },
+ .name = "atomisp",
+ .id_table = mfld_isp_pci_tbl,
+ .probe = mfld_isp_pci_probe,
+ .remove = mfld_isp_pci_remove,
+#ifdef CONFIG_PM
+ .suspend = mfld_isp_pci_suspend,
+ .resume = mfld_isp_pci_resume,
+#endif
+};
+
+static int __init mfld_isp_init(void)
+{
+ mfld_isp_dbg(KERN_INFO, "Init ATOM ISP device driver,"
+ " version: %s\n", DRIVER_VERSION_STR);
+ return pci_register_driver(&mfld_isp_pci_driver);
+}
+
+static void __exit mfld_isp_exit(void)
+{
+ mfld_isp_dbg(KERN_INFO, "Exit ATOM ISP device driver\n");
+ pci_unregister_driver(&mfld_isp_pci_driver);
+}
+
+late_initcall(mfld_isp_init);
+module_exit(mfld_isp_exit);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
--
1.5.4.3
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