[Meego-kernel] [MFLD Camera - PATCH v6 5/9] Medfield Camera Image ISP driver HW abstract layer.
Wang, Wen W
wen.w.wang at intel.com
Thu Dec 23 06:37:35 PST 2010
>From df396b2af391603a78cd1bf2502963359db5d3e8 Mon Sep 17 00:00:00 2001
From: Wen Wang <wen.w.wang at intel.com>
Date: Fri, 24 Dec 2010 02:07:22 +0800
Subject: [PATCH] Medfield Camera Image ISP driver HW abstract layer
This patch includes hardware abstraction layer for Medfield camera image ISP
driver. It provides functions and defines to access hardware components inside
the ISP
Signed-off-by: Wen Wang <wen.w.wang at intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
---
.../media/video/atomisp/hrt/hive_isp_css_ddr_hrt.c | 317 +++
.../media/video/atomisp/hrt/hive_isp_css_mm_hrt.c | 141 ++
drivers/media/video/atomisp/include/css_hrt/bits.h | 110 +
.../include/css_hrt/css_receiver_ahb_defs.h | 215 ++
drivers/media/video/atomisp/include/css_hrt/defs.h | 44 +
.../video/atomisp/include/css_hrt/dma_v1_defs.h | 244 ++
.../media/video/atomisp/include/css_hrt/embed.h | 42 +
.../media/video/atomisp/include/css_hrt/gdc_defs.h | 98 +
.../video/atomisp/include/css_hrt/gp_regs_defs.h | 29 +
.../include/css_hrt/hive_isp_css_custom_host_hrt.h | 90 +
.../atomisp/include/css_hrt/hive_isp_css_ddr_hrt.c | 358 +++
.../atomisp/include/css_hrt/hive_isp_css_ddr_hrt.h | 143 ++
.../atomisp/include/css_hrt/hive_isp_css_defs.h | 196 ++
.../include/css_hrt/hive_isp_css_host_ids_hrt.h | 66 +
.../atomisp/include/css_hrt/hive_isp_css_if_hrt.h | 42 +
.../include/css_hrt/hive_isp_css_irq_types_hrt.h | 77 +
.../atomisp/include/css_hrt/hive_isp_css_mm_hrt.c | 237 ++
.../atomisp/include/css_hrt/hive_isp_css_mm_hrt.h | 63 +
.../css_hrt/hive_isp_css_program_load_hrt.h | 154 ++
.../hive_isp_css_streaming_monitors_types_hrt.h | 71 +
.../hive_isp_css_streaming_to_mipi_types_hrt.h | 36 +
.../media/video/atomisp/include/css_hrt/if_defs.h | 72 +
.../atomisp/include/css_hrt/irq_controller_defs.h | 35 +
.../include/css_hrt/isp2300_medfield_params.h | 177 ++
.../video/atomisp/include/css_hrt/master_port.h | 148 ++
.../media/video/atomisp/include/css_hrt/mmu_defs.h | 31 +
.../media/video/atomisp/include/css_hrt/sp.map.h | 2349 ++++++++++++++++++++
.../media/video/atomisp/include/css_hrt/sp_hrt.h | 31 +
.../include/css_hrt/streaming_to_mipi_defs.h | 36 +
.../media/video/atomisp/include/css_hrt/vector.h | 110 +
30 files changed, 5762 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/video/atomisp/hrt/hive_isp_css_ddr_hrt.c
create mode 100644 drivers/media/video/atomisp/hrt/hive_isp_css_mm_hrt.c
create mode 100644 drivers/media/video/atomisp/include/css_hrt/bits.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/css_receiver_ahb_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/dma_v1_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/embed.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/gdc_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/gp_regs_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_custom_host_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.c
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_host_ids_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_if_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_irq_types_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.c
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_program_load_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_monitors_types_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_to_mipi_types_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/if_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/irq_controller_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/isp2300_medfield_params.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/master_port.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/mmu_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/sp.map.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/sp_hrt.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/streaming_to_mipi_defs.h
create mode 100644 drivers/media/video/atomisp/include/css_hrt/vector.h
diff --git a/drivers/media/video/atomisp/hrt/hive_isp_css_ddr_hrt.c b/drivers/media/video/atomisp/hrt/hive_isp_css_ddr_hrt.c
new file mode 100644
index 0000000..1b663c2
--- /dev/null
+++ b/drivers/media/video/atomisp/hrt/hive_isp_css_ddr_hrt.c
@@ -0,0 +1,317 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <vector.h>
+#ifdef HRT_CSIM
+#include <error.h>
+#endif
+#include "hive_isp_css_defs.h"
+#include "hive_isp_css_ddr_hrt.h"
+#include "hive_isp_css_mm_hrt.h"
+#include "mfldisp_internal.h"
+#define BYTES_PER_XWORD (HIVE_ISP_DDR_WORD_BITS/8)
+#define ceil_div(a, b) (((a)+(b)-1)/(b))
+
+struct dma_spec_s {
+ unsigned int num_elems;
+ unsigned int elem_bits;
+};
+
+static struct dma_spec_s specs[] = HIVE_ISP_DDR_DMA_SPECS;
+static unsigned int num_specs = sizeof(specs) / sizeof(*specs);
+
+static unsigned int
+dma_num_elems_to_elem_width(unsigned int num_elems, unsigned int *bits)
+{
+ unsigned int i;
+ for (i = 0; i < num_specs; i++) {
+ if (specs[i].num_elems == num_elems) {
+ *bits = specs[i].elem_bits;
+ return 1;
+ }
+ }
+ v4l2_printk(KERN_WARNING, &isp_dev,
+ "cannot translate number of elements (%d) to"
+ "element bits in dma",
+ num_elems);
+ return 0;
+}
+
+static unsigned int
+dma_elem_width_to_num_elems(unsigned int bits, unsigned int *num_elems)
+{
+ unsigned int i;
+ for (i = 0; i < num_specs; i++) {
+ if (specs[i].elem_bits == bits) {
+ *num_elems = specs[i].num_elems;
+ return 1;
+ }
+ }
+ v4l2_printk(KERN_WARNING, &isp_dev,
+ "cannot translate element width (%u) to number"
+ " of elements per word",
+ *num_elems);
+ return 0;
+}
+
+unsigned int
+hrt_isp_css_stride_of_image_in_ddr(unsigned int width,
+ unsigned int bits_per_element)
+{
+ unsigned int elems_per_xword, xwords_per_line;
+
+ if (dma_elem_width_to_num_elems(bits_per_element, &elems_per_xword) ==
+ 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+ return xwords_per_line * BYTES_PER_XWORD;
+}
+
+unsigned int
+hrt_isp_css_sizeof_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ return hrt_isp_css_stride_of_image_in_ddr(width,
+ bits_per_element) * height;
+}
+
+void *
+hrt_isp_css_alloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_alloc(bytes);
+}
+
+void *
+hrt_isp_css_calloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_calloc(bytes);
+}
+
+unsigned int
+hrt_isp_css_read_image_from_ddr(unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend,
+ void *virt_addr)
+{
+ unsigned int i, j, k, elem_bits, xwords_per_line;
+ char xword_buf[BYTES_PER_XWORD];
+ /* this is the maximum number of elements in an xword */
+ int elem_buf[BYTES_PER_XWORD];
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return 0;
+ if (elem_bits == 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+
+ for (i = 0; i < height; i++) {
+ unsigned int elems_in_line = width;
+ for (j = 0; j < xwords_per_line; j++) {
+ unsigned int elems_in_word = elems_per_xword;
+ if (elems_in_word > elems_in_line)
+ elems_in_word = elems_in_line;
+ hrt_isp_css_mm_load(virt_addr, xword_buf,
+ BYTES_PER_XWORD);
+ _hrt_decode_vector(xword_buf, elem_buf, elem_bits,
+ elem_bits, elems_per_xword,
+ sign_extend);
+ for (k = 0; k < elems_in_word;
+ k++, elems_in_line--, img_buf++)
+ *img_buf = (unsigned short)elem_buf[k];
+ virt_addr += BYTES_PER_XWORD;
+ }
+ }
+
+ return 1;
+}
+
+unsigned int
+hrt_isp_css_write_image_to_ddr(const unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend,
+ void *virt_addr)
+{
+ unsigned int i, j, k, elem_bits, xwords_per_line;
+ char xword_buf[BYTES_PER_XWORD];
+ int elem_buf[BYTES_PER_XWORD];
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return 0;
+ if (elem_bits == 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+
+ for (i = 0; i < height; i++) {
+ unsigned int elems_in_line = width;
+ for (j = 0; j < xwords_per_line; j++) {
+ unsigned int elems_in_word = elems_per_xword;
+ if (elems_in_word > elems_in_line)
+ elems_in_word = elems_in_line;
+ for (k = 0; k < elems_in_word;
+ k++, elems_in_line--, img_buf++)
+ elem_buf[k] = *img_buf;
+ _hrt_encode_vector(elem_buf, xword_buf, elem_bits,
+ elem_bits, elems_per_xword,
+ sign_extend);
+ hrt_isp_css_mm_store(virt_addr, xword_buf,
+ BYTES_PER_XWORD);
+ virt_addr += BYTES_PER_XWORD;
+ }
+ }
+
+ return 1;
+}
+
+void *
+hrt_isp_css_alloc_gdc_lut_in_ddr(void)
+{
+ return hrt_isp_css_mm_alloc(HRT_GDC_LUT_BYTES);
+}
+
+void
+hrt_isp_css_write_gdc_lut_to_ddr(short lut[4][HRT_GDC_N], void *virt_addr)
+{
+ unsigned int i;
+ for (i = 0; i < HRT_GDC_N; i++) {
+ unsigned int entry_0 = lut[0][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_1 = lut[1][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_2 = lut[2][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_3 = lut[3][i] & HRT_GDC_BCI_COEF_MASK,
+ word_0 = entry_0 | (entry_1 << HRT_GDC_BCI_COEF_BITS),
+ word_1 = entry_2 | (entry_3 << HRT_GDC_BCI_COEF_BITS);
+ hrt_isp_css_mm_store_int(virt_addr, word_0);
+ virt_addr += 4;
+ hrt_isp_css_mm_store_int(virt_addr, word_1);
+ virt_addr += 4;
+ }
+}
+
+unsigned int
+hrt_isp_css_read_unsigned(unsigned short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(source_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_read_image_from_ddr(target, width, height,
+ elems_per_xword, 0, source);
+}
+
+unsigned int
+hrt_isp_css_read_signed(short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(source_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_read_image_from_ddr((unsigned short *)target, width,
+ height, elems_per_xword, 1,
+ source);
+}
+
+unsigned int
+hrt_isp_css_write_unsigned(const unsigned short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(target_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_write_image_to_ddr(source, width, height,
+ elems_per_xword, 0, target);
+}
+
+unsigned int
+hrt_isp_css_write_signed(const short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(target_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_write_image_to_ddr((const unsigned short *)source,
+ width, height, elems_per_xword, 1,
+ target);
+}
+
+void *
+hrt_isp_css_alloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ size_t bytes;
+
+ bytes =
+ hrt_isp_css_sizeof_image_in_ddr(width, height, bits_per_element);
+ return hrt_isp_css_mm_alloc(bytes);
+}
+
+void *
+hrt_isp_css_calloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ size_t bytes;
+
+ bytes =
+ hrt_isp_css_sizeof_image_in_ddr(width, height, bits_per_element);
+ return hrt_isp_css_mm_calloc(bytes);
+}
diff --git a/drivers/media/video/atomisp/hrt/hive_isp_css_mm_hrt.c b/drivers/media/video/atomisp/hrt/hive_isp_css_mm_hrt.c
new file mode 100644
index 0000000..48a6c50
--- /dev/null
+++ b/drivers/media/video/atomisp/hrt/hive_isp_css_mm_hrt.c
@@ -0,0 +1,141 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <hmm/hmm.h>
+
+/* not sure if we need these two for page related macros,
+ * need to double check */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include "mfldisp_internal.h"
+
+#define __page_align(size) (((size) + (PAGE_SIZE-1)) & (~(PAGE_SIZE-1)))
+
+static unsigned init_done;
+void hrt_isp_css_mm_init(void)
+{
+ v4l2_printk(KERN_DEBUG, &isp_dev, "hrt_isp_css_mm_init...\n");
+ hmm_init();
+ init_done = 1;
+ v4l2_printk(KERN_DEBUG, &isp_dev,
+ "hrt_isp_css_mm_init... done\n");
+}
+
+void hrt_isp_css_mm_load(void *virt_addr, void *data, size_t bytes)
+{
+ hmm_load(virt_addr, data, bytes);
+}
+
+void hrt_isp_css_mm_store(void *virt_addr, const void *data, size_t bytes)
+{
+ hmm_store(virt_addr, data, bytes);
+}
+
+void hrt_isp_css_mm_free(void *virt_addr)
+{
+ hmm_free(virt_addr);
+}
+
+void hrt_isp_css_mm_clear(void)
+{
+ if (init_done) {
+ hmm_cleanup();
+ init_done = 0;
+ }
+}
+
+static unsigned int my_userptr, my_num_pages;
+void hrt_isp_css_mm_set_user_ptr(unsigned int userptr, unsigned int num_pages)
+{
+ my_userptr = userptr;
+ my_num_pages = num_pages;
+}
+
+void *hrt_isp_css_mm_alloc(size_t bytes)
+{
+ if (!init_done)
+ hrt_isp_css_mm_init();
+
+ if (my_userptr == 0)
+ return (void *)hmm_alloc(bytes, HMM_BO_PRIVATE, 0, 0);
+ else {
+ if (my_num_pages < ((__page_align(bytes)) >> PAGE_SHIFT))
+ v4l2_printk(KERN_ERR, &isp_dev,
+ "user space memory size is less"
+ " than the expected size..\n");
+ else if (my_num_pages > ((__page_align(bytes)) >> PAGE_SHIFT))
+ v4l2_printk(KERN_ERR, &isp_dev,
+ "user space memory size is"
+ " large than the expected size..\n");
+ return (void *)hmm_alloc(bytes, HMM_BO_USER, 0, my_userptr);
+ }
+}
+
+void *hrt_isp_css_mm_calloc(size_t bytes)
+{
+ void *ptr = hrt_isp_css_mm_alloc(bytes);
+ if (!ptr)
+ hmm_set(ptr, 0, bytes);
+ return ptr;
+}
+
+int hrt_isp_css_mm_load_int(void *virt_addr)
+{
+ int v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+short hrt_isp_css_mm_load_short(void *virt_addr)
+{
+ short v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+char hrt_isp_css_mm_load_char(void *virt_addr)
+{
+ char v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+void hrt_isp_css_mm_store_char(void *virt_addr, char data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void hrt_isp_css_mm_store_short(void *virt_addr, short data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void hrt_isp_css_mm_store_int(void *virt_addr, int data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void *hrt_isp_css_virt_to_phys(void *virt_addr)
+{
+ return (void *)hmm_virt_to_phys(virt_addr);
+}
diff --git a/drivers/media/video/atomisp/include/css_hrt/bits.h b/drivers/media/video/atomisp/include/css_hrt/bits.h
new file mode 100644
index 0000000..7ba07ee
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/bits.h
@@ -0,0 +1,110 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HRT_BITS_H_
+#define _HRT_BITS_H_
+
+#include "defs.h"
+
+#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
+#define _hrt_ones_0x0 0x00000000U
+#define _hrt_ones_0x1 0x00000001U
+#define _hrt_ones_0x2 0x00000003U
+#define _hrt_ones_0x3 0x00000007U
+#define _hrt_ones_0x4 0x0000000FU
+#define _hrt_ones_0x5 0x0000001FU
+#define _hrt_ones_0x6 0x0000003FU
+#define _hrt_ones_0x7 0x0000007FU
+#define _hrt_ones_0x8 0x000000FFU
+#define _hrt_ones_0x9 0x000001FFU
+#define _hrt_ones_0xA 0x000003FFU
+#define _hrt_ones_0xB 0x000007FFU
+#define _hrt_ones_0xC 0x00000FFFU
+#define _hrt_ones_0xD 0x00001FFFU
+#define _hrt_ones_0xE 0x00003FFFU
+#define _hrt_ones_0xF 0x00007FFFU
+#define _hrt_ones_0x10 0x0000FFFFU
+#define _hrt_ones_0x11 0x0001FFFFU
+#define _hrt_ones_0x12 0x0003FFFFU
+#define _hrt_ones_0x13 0x0007FFFFU
+#define _hrt_ones_0x14 0x000FFFFFU
+#define _hrt_ones_0x15 0x001FFFFFU
+#define _hrt_ones_0x16 0x003FFFFFU
+#define _hrt_ones_0x17 0x007FFFFFU
+#define _hrt_ones_0x18 0x00FFFFFFU
+#define _hrt_ones_0x19 0x01FFFFFFU
+#define _hrt_ones_0x1A 0x03FFFFFFU
+#define _hrt_ones_0x1B 0x07FFFFFFU
+#define _hrt_ones_0x1C 0x0FFFFFFFU
+#define _hrt_ones_0x1D 0x1FFFFFFFU
+#define _hrt_ones_0x1E 0x3FFFFFFFU
+#define _hrt_ones_0x1F 0x7FFFFFFFU
+#define _hrt_ones_0x20 0xFFFFFFFFU
+
+#define _hrt_ones_0 _hrt_ones_0x0
+#define _hrt_ones_1 _hrt_ones_0x1
+#define _hrt_ones_2 _hrt_ones_0x2
+#define _hrt_ones_3 _hrt_ones_0x3
+#define _hrt_ones_4 _hrt_ones_0x4
+#define _hrt_ones_5 _hrt_ones_0x5
+#define _hrt_ones_6 _hrt_ones_0x6
+#define _hrt_ones_7 _hrt_ones_0x7
+#define _hrt_ones_8 _hrt_ones_0x8
+#define _hrt_ones_9 _hrt_ones_0x9
+#define _hrt_ones_10 _hrt_ones_0xA
+#define _hrt_ones_11 _hrt_ones_0xB
+#define _hrt_ones_12 _hrt_ones_0xC
+#define _hrt_ones_13 _hrt_ones_0xD
+#define _hrt_ones_14 _hrt_ones_0xE
+#define _hrt_ones_15 _hrt_ones_0xF
+#define _hrt_ones_16 _hrt_ones_0x10
+#define _hrt_ones_17 _hrt_ones_0x11
+#define _hrt_ones_18 _hrt_ones_0x12
+#define _hrt_ones_19 _hrt_ones_0x13
+#define _hrt_ones_20 _hrt_ones_0x14
+#define _hrt_ones_21 _hrt_ones_0x15
+#define _hrt_ones_22 _hrt_ones_0x16
+#define _hrt_ones_23 _hrt_ones_0x17
+#define _hrt_ones_24 _hrt_ones_0x18
+#define _hrt_ones_25 _hrt_ones_0x19
+#define _hrt_ones_26 _hrt_ones_0x1A
+#define _hrt_ones_27 _hrt_ones_0x1B
+#define _hrt_ones_28 _hrt_ones_0x1C
+#define _hrt_ones_29 _hrt_ones_0x1D
+#define _hrt_ones_30 _hrt_ones_0x1E
+#define _hrt_ones_31 _hrt_ones_0x1F
+#define _hrt_ones_32 _hrt_ones_0x20
+
+#define _hrt_mask(b, n) (_hrt_ones(n) << (b))
+#define _hrt_get_bits(w, b, n) (((w) >> (b)) & _hrt_ones(n))
+#define _hrt_set_bits(w, b, n, v) \
+(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
+#define _hrt_get_bit(w, b) \
+(((w) >> (b)) & 1)
+#define _hrt_set_bit(w, b, v) \
+(((w) & (~(1 << (b)))) | (((v)&1) << (b)))
+#define _hrt_set_lower_half(w, v) \
+_hrt_set_bits(w, 0, 16, v)
+#define _hrt_set_upper_half(w, v) \
+_hrt_set_bits(w, 16, 16, v)
+
+#endif /* _HRT_BITS_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/css_receiver_ahb_defs.h b/drivers/media/video/atomisp/include/css_hrt/css_receiver_ahb_defs.h
new file mode 100644
index 0000000..73cf498
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/css_receiver_ahb_defs.h
@@ -0,0 +1,215 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _css_receiver_ahb_defs_h_
+#define _css_receiver_ahb_defs_h_
+
+#define CSS_RECEIVER_DATA_WIDTH 8
+#define CSS_RECEIVER_RX_TRIG 4
+#define CSS_RECEIVER_RF_WORD 32
+#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
+#define CSS_RECEIVER_CSI_RF_ADDR 4
+#define CSS_RECEIVER_DATA_OUT 12
+#define CSS_RECEIVER_CHN_NO 2
+#define CSS_RECEIVER_DWORD_CNT 11
+#define CSS_RECEIVER_FORMAT_TYP 5
+#define CSS_RECEIVER_HRESPONSE 2
+#define CSS_RECEIVER_STATE_WIDTH 3
+#define CSS_RECEIVER_FIFO_DAT 32
+#define CSS_RECEIVER_CNT_VAL 2
+#define CSS_RECEIVER_PRED10_VAL 10
+#define CSS_RECEIVER_PRED12_VAL 12
+#define CSS_RECEIVER_CNT_WIDTH 8
+#define CSS_RECEIVER_WORD_CNT 16
+#define CSS_RECEIVER_PIXEL_LEN 6
+#define CSS_RECEIVER_PIXEL_CNT 5
+#define CSS_RECEIVER_COMP_8_BIT 8
+#define CSS_RECEIVER_COMP_7_BIT 7
+#define CSS_RECEIVER_COMP_6_BIT 6
+#define CSS_RECEIVER_GEN_SHORT_DATA_WIDTH 16
+#define CSS_RECEIVER_GEN_SHORT_CH_ID_WIDTH 2
+#define CSS_RECEIVER_GEN_SHORT_FMT_TYPE_WIDTH 3
+#define CSS_RECEIVER_GEN_SHORT_STR_REAL_WIDTH \
+ (CSS_RECEIVER_GEN_SHORT_DATA_WIDTH + \
+ CSS_RECEIVER_GEN_SHORT_CH_ID_WIDTH + \
+ CSS_RECEIVER_GEN_SHORT_FMT_TYPE_WIDTH)
+/* use 32 to be compatible with streaming monitor!
+ * MSB's of interface are tied to '0'.
+ */
+#define CSS_RECEIVER_GEN_SHORT_STR_WIDTH 32
+
+/* division of gen_short data, ch_id and fmt_type over
+ * streaming data interface.
+ */
+#define CSS_RECEIVER_GEN_SHORT_STR_DATA_BIT_LSB 0
+#define CSS_RECEIVER_GEN_SHORT_STR_FMT_TYPE_BIT_LSB \
+ (CSS_RECEIVER_GEN_SHORT_STR_DATA_BIT_LSB + \
+ CSS_RECEIVER_GEN_SHORT_DATA_WIDTH)
+#define CSS_RECEIVER_GEN_SHORT_STR_CH_ID_BIT_LSB \
+ (CSS_RECEIVER_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + \
+ CSS_RECEIVER_GEN_SHORT_FMT_TYPE_WIDTH)
+#define CSS_RECEIVER_GEN_SHORT_STR_DATA_BIT_MSB \
+ (CSS_RECEIVER_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
+#define CSS_RECEIVER_GEN_SHORT_STR_FMT_TYPE_BIT_MSB \
+ (CSS_RECEIVER_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
+#define CSS_RECEIVER_GEN_SHORT_STR_CH_ID_BIT_MSB \
+ (CSS_RECEIVER_GEN_SHORT_STR_REAL_WIDTH - 1)
+
+#define _HRT_CSS_RECEIVER_AHB_REG_ALIGN 4
+
+#define hrt_css_receiver_ahb_4_lane_port_offset 0x100
+#define hrt_css_receiver_ahb_1_lane_port_offset 0x200
+
+#define _HRT_CSS_RECEIVER_AHB_DEVICE_READY_REG_IDX 0
+#define _HRT_CSS_RECEIVER_AHB_IRQ_STATUS_REG_IDX 1
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ENABLE_REG_IDX 2
+#define _HRT_CSS_RECEIVER_AHB_CSI2_FUNC_PROG_REG_IDX 3
+#define _HRT_CSS_RECEIVER_AHB_INIT_COUNT_REG_IDX 4
+#define _HRT_CSS_RECEIVER_AHB_COMP_FORMAT_REG_IDX 5
+#define _HRT_CSS_RECEIVER_AHB_COMP_PREDICT_REG_IDX 6
+#define _HRT_CSS_RECEIVER_AHB_FS_TO_LS_DELAY_REG_IDX 7
+#define _HRT_CSS_RECEIVER_AHB_LS_TO_DATA_DELAY_REG_IDX 8
+#define _HRT_CSS_RECEIVER_AHB_DATA_TO_LE_DELAY_REG_IDX 9
+#define _HRT_CSS_RECEIVER_AHB_LE_TO_FE_DELAY_REG_IDX 10
+#define _HRT_CSS_RECEIVER_AHB_FE_TO_FS_DELAY_REG_IDX 11
+#define _HRT_CSS_RECEIVER_AHB_LE_TO_LS_DELAY_REG_IDX 12
+#define _HRT_CSS_RECEIVER_AHB_TWO_PIXEL_EN_REG_IDX 13
+
+/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
+#define _HRT_CSS_RECEIVER_AHB_IRQ_OVERRUN_BIT 0
+#define _HRT_CSS_RECEIVER_AHB_IRQ_RESERVED_BIT 1
+#define _HRT_CSS_RECEIVER_AHB_IRQ_SLEEP_MODE_ENTRY_BIT 2
+#define _HRT_CSS_RECEIVER_AHB_IRQ_SLEEP_MODE_EXIT_BIT 3
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_SOT_HS_BIT 4
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_SOT_SYNC_HS_BIT 5
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_CONTROL_BIT 6
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_DOUBLE_BIT 7
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_CORRECTED_BIT 8
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_NO_CORRECTION_BIT 9
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_CRC_BIT 10
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ID_BIT 11
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_FRAME_SYNC_BIT 12
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_FRAME_DATA_BIT 13
+#define _HRT_CSS_RECEIVER_AHB_IRQ_DATA_TIMEOUT_BIT 14
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ESCAPE_BIT 15
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_LINE_SYNC_BIT 16
+
+#define _HRT_CSS_RECEIVER_AHB_IRQ_OVERRUN_CAUSE_\
+ "Fifo Overrun"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_RESERVED_CAUSE_ \
+ "Reserved"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_SLEEP_MODE_ENTRY_CAUSE_ \
+ "Sleep mode entry"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_SLEEP_MODE_EXIT_CAUSE_ \
+ "Sleep mode exit"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_SOT_HS_CAUSE_ \
+ "Error high speed SOT"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_SOT_SYNC_HS_CAUSE_ \
+ "Error high speed sync SOT"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_CONTROL_CAUSE_ \
+ "Error control"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_DOUBLE_CAUSE_ \
+ "Error correction double bit"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_CORRECTED_CAUSE_ \
+ "Error correction single bit"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ \
+ "No error"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_CRC_CAUSE_ \
+ "Error cyclic redundancy check"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ID_CAUSE_ \
+ "Error id"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_FRAME_SYNC_CAUSE_ \
+ "Error frame sync"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_FRAME_DATA_CAUSE_ \
+ "Error frame data"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_DATA_TIMEOUT_CAUSE_ \
+ "Data time-out"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_ESCAPE_CAUSE_ \
+ "Error escape"
+#define _HRT_CSS_RECEIVER_AHB_IRQ_ERR_LINE_SYNC_CAUSE_ \
+ "Error line sync"
+
+/* Bits for CSI2_FUNC_PROG register */
+#define _HRT_CSS_RECEIVER_AHB_CSI2_NUM_DATA_LANES_IDX 0
+#define _HRT_CSS_RECEIVER_AHB_CSI2_NUM_DATA_LANES_BITS 3
+#define _HRT_CSS_RECEIVER_AHB_CSI2_DATA_TIMEOUT_IDX \
+ (_HRT_CSS_RECEIVER_AHB_CSI2_NUM_DATA_LANES_IDX + \
+ _HRT_CSS_RECEIVER_AHB_CSI2_NUM_DATA_LANES_BITS)
+#define _HRT_CSS_RECEIVER_AHB_CSI2_DATA_TIMEOUT_BITS 29
+
+/* Bits for INIT_COUNT register */
+#define _HRT_CSS_RECEIVER_AHB_INIT_TIMER_IDX 0
+#define _HRT_CSS_RECEIVER_AHB_INIT_TIMER_BITS 16
+
+/* Bits for COMP_FORMAT register, this selects the compression data format */
+#define _HRT_CSS_RECEIVER_AHB_COMP_RAW_BITS_IDX 0
+#define _HRT_CSS_RECEIVER_AHB_COMP_RAW_BITS_BITS 8
+#define _HRT_CSS_RECEIVER_AHB_COMP_NUM_BITS_IDX \
+ (_HRT_CSS_RECEIVER_AHB_COMP_RAW_BITS_IDX + \
+ _HRT_CSS_RECEIVER_AHB_COMP_RAW_BITS_BITS)
+#define _HRT_CSS_RECEIVER_AHB_COMP_NUM_BITS_BITS 8
+
+/* Bits for COMP_PREDICT register, this selects the predictor algorithm */
+#define _HRT_CSS_RECEIVER_AHB_PREDICT_NO_COMP 0
+#define _HRT_CSS_RECEIVER_AHB_PREDICT_1 1
+#define _HRT_CSS_RECEIVER_AHB_PREDICT_2 2
+
+/* Number of bits used for the delay registers */
+#define _HRT_CSS_RECEIVER_AHB_DELAY_BITS 8
+
+/* These hsync and vsync values are for HSS simulation only */
+#define _HRT_CSS_RECEIVER_AHB_HSYNC_VAL (1<<16)
+#define _HRT_CSS_RECEIVER_AHB_VSYNC_VAL (1<<17)
+
+/* Definition of format_types */
+/* !! Changes here should be copied to
+ * systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !!
+ */
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RGB888 0
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RGB555 1
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RGB444 2
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RGB565 3
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RGB666 4
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW8 5
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW10 6
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW6 7
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW7 8
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW12 9
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_RAW14 10
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV420_8 11
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV420_10 12
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV422_8 13
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV422_10 14
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_1 15
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV420_8L 16
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_Emb 17
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_2 18
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_3 19
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_4 20
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_5 21
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_6 22
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_7 23
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_USR_DEF_8 24
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV420_8_CSPS 25
+#define _HRT_CSS_RECEIVER_AHB_FMT_TYPE_YUV420_10_CSPS 26
+
+#endif /* _css_receiver_ahb_defs_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/defs.h b/drivers/media/video/atomisp/include/css_hrt/defs.h
new file mode 100644
index 0000000..7389173
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/defs.h
@@ -0,0 +1,44 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HRT_DEFS_H_
+#define _HRT_DEFS_H_
+
+#ifndef HRTCAT
+#define _HRTCAT(m, n) m##n
+#define HRTCAT(m, n) _HRTCAT(m, n)
+#endif
+
+#ifndef HRTSTR
+#define _HRTSTR(x) #x
+#define HRTSTR(x) _HRTSTR(x)
+#endif
+
+#ifndef HRTMIN
+#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef HRTMAX
+#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#endif /* _HRT_DEFS_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/dma_v1_defs.h b/drivers/media/video/atomisp/include/css_hrt/dma_v1_defs.h
new file mode 100644
index 0000000..8a383e8
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/dma_v1_defs.h
@@ -0,0 +1,244 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _dma_v1_defs_h
+#define _dma_v1_defs_h
+
+/* if this file is included from a C source file, you need to include
+ * <hrt/bits.h> first. We cannot include that here because this file is
+ * also included from CHDL sources which do not have access to HRT.
+ */
+#define _DMA_V1_NUM_CHANNELS_ID MaxNumChannels
+#define _DMA_V1_CONNECTIONS_ID Connections
+#define _DMA_V1_DEV_ELEM_WIDTHS_ID DevElemWidths
+#define _DMA_V1_DEV_FIFO_DEPTH_ID DevFifoDepth
+#define _DMA_V1_DEV_FIFO_RD_LAT_ID DevFifoRdLat
+#define _DMA_V1_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
+#define _DMA_V1_DEV_2_CIO_ID DevConnectedToCIO
+#define _DMA_V1_DEV_HAS_CRUN_ID CRunMasters
+#define _DMA_V1_CONN_GROUPS_ID ConnectionGroups
+#define _DMA_V1_CONN_GROUP_FIFO_DEPTH_ID ConnectionGroupFifoDepth
+#define _DMA_V1_CONN_GROUP_FIFO_RD_LAT_ID ConnectionGroupFifoRdLat
+#define _DMA_V1_CONN_GROUP_FIFO_LAT_BYPASS_ID ConnectionGroupFifoRdLatBypass
+
+#define _DMA_V1_REG_ALIGN 4
+#define _DMA_V1_REG_ADDR_BITS 2
+
+/* Command word */
+#define _DMA_CMD_IDX 0
+#define _DMA_CMD_BITS 4
+#define _DMA_CHANNEL_IDX (_DMA_CMD_IDX + _DMA_CMD_BITS)
+#define _DMA_CHANNEL_BITS 8
+#define _DMA_PARAM_IDX (_DMA_CHANNEL_IDX + _DMA_CHANNEL_BITS)
+#define _DMA_PARAM_BITS 4
+#define _DMA_CRUN_IDX (_DMA_PARAM_IDX + _DMA_PARAM_BITS)
+#define _DMA_CRUN_BITS 1
+
+/* Packing setup word */
+#define _DMA_CONNECTION_IDX 0
+#define _DMA_CONNECTION_BITS 8
+#define _DMA_EXTENSION_IDX (_DMA_CONNECTION_IDX + _DMA_CONNECTION_BITS)
+#define _DMA_EXTENSION_BITS 4
+#define _DMA_ELEM_ORDER_IDX (_DMA_EXTENSION_IDX + _DMA_EXTENSION_BITS)
+#define _DMA_ELEM_ORDER_BITS 4
+
+/* Elements packing word */
+#define _DMA_ELEMENTS_IDX 0
+#define _DMA_ELEMENTS_BITS 12
+#define _DMA_LEFT_CROPPING_IDX (_DMA_ELEMENTS_IDX + _DMA_ELEMENTS_BITS)
+#define _DMA_LEFT_CROPPING_BITS 12
+
+#define _DMA_WIDTH_IDX 0
+#define _DMA_WIDTH_BITS 16
+
+#define _DMA_HEIGHT_IDX 0
+#define _DMA_HEIGHT_BITS 16
+
+#define _DMA_STRIDE_IDX 0
+#define _DMA_STRIDE_BITS 32
+
+/* Command IDs */
+#define _DMA_READ_COMMAND 0
+#define _DMA_WRITE_COMMAND 1
+#define _DMA_CONFIG_CHANNEL_COMMAND 2
+#define _DMA_SET_CHANNEL_PARAM_COMMAND 3
+#define _DMA_INIT_COMMAND 8
+#define _DMA_RESET_COMMAND 15
+
+/* Channel Parameter IDs */
+#define _DMA_PACKING_SETUP_PARAM 0
+#define _DMA_STRIDE_A_PARAM 1
+#define _DMA_ELEM_CROPPING_A_PARAM 2
+#define _DMA_WIDTH_A_PARAM 3
+#define _DMA_STRIDE_B_PARAM 4
+#define _DMA_ELEM_CROPPING_B_PARAM 5
+#define _DMA_WIDTH_B_PARAM 6
+#define _DMA_HEIGHT_PARAM 7
+
+/* Parameter Constants */
+#define _DMA_ZERO_EXTEND 0
+#define _DMA_SIGN_EXTEND 1
+#define _DMA_REVERSE_ELEMS 1
+#define _DMA_KEEP_ELEM_ORDER 0
+
+ /* SLAVE address map */
+#define _DMA_SEL_FSM_CMD 0
+#define _DMA_SEL_CH_REG 1
+#define _DMA_SEL_CONN_GROUP 2
+#define _DMA_SEL_DEV_INTERF 3
+#define _DMA_SEL_RESET 15
+
+#define _DMA_RESET_TOKEN 0xDEADCAFE
+
+#define _DMA_SEL_CONN_CMD 0
+#define _DMA_SEL_CONN_ADDRESS_A 1
+#define _DMA_SEL_CONN_ADDRESS_B 2
+#define _DMA_SEL_FSM_CONN_CTRL 3
+#define _DMA_SEL_FSM_PACK 4
+#define _DMA_SEL_FSM_REQ 5
+#define _DMA_SEL_FSM_WR 6
+
+#define _DMA_ADDR_SEL_COMP_IDX 12
+#define _DMA_ADDR_SEL_COMP_BITS 4
+#define _DMA_ADDR_SEL_CH_REG_IDX 2
+#define _DMA_ADDR_SEL_CH_REG_BITS 6
+#define _DMA_ADDR_SEL_PARAM_IDX 8
+#define _DMA_ADDR_SEL_PARAM_BITS 4
+
+#define _DMA_ADDR_SEL_GROUP_IDX 2
+#define _DMA_ADDR_SEL_GROUP_BITS 3
+#define _DMA_ADDR_SEL_GROUP_COMP_IDX 5
+#define _DMA_ADDR_SEL_GROUP_COMP_BITS 3
+#define _DMA_ADDR_SEL_GROUP_COMP_INFO_IDX 8
+#define _DMA_ADDR_SEL_GROUP_COMP_INFO_BITS 4
+
+#define _DMA_ADDR_SEL_DEV_INTERF_IDX_IDX 2
+#define _DMA_ADDR_SEL_DEV_INTERF_IDX_BITS 6
+#define _DMA_ADDR_SEL_DEV_INTERF_INFO_IDX 8
+#define _DMA_ADDR_SEL_DEV_INTERF_INFO_BITS 4
+
+#define _DMA_FSM_GROUP_CMD_IDX 0
+#define _DMA_FSM_GROUP_ADDR_A_IDX 1
+#define _DMA_FSM_GROUP_ADDR_B_IDX 2
+#define _DMA_FSM_GROUP_FSM_CTRL_IDX 3
+#define _DMA_FSM_GROUP_FSM_PACK_IDX 4
+#define _DMA_FSM_GROUP_FSM_REQ_IDX 5
+#define _DMA_FSM_GROUP_FSM_WR_IDX 6
+
+#define _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX 0
+#define _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
+#define _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
+#define _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
+#define _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
+#define _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
+#define _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
+#define _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
+#define _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_REV_IDX 15
+
+#define _DMA_FSM_GROUP_FSM_PACK_STATE_IDX 0
+#define _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
+#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
+#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
+
+#define _DMA_FSM_GROUP_FSM_REQ_STATE_IDX 0
+#define _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
+#define _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
+
+#define _DMA_FSM_GROUP_FSM_WR_STATE_IDX 0
+#define _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
+#define _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
+
+#define _DMA_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
+#define _DMA_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
+#define _DMA_DEV_INTERF_FIFO_STATUS_IDX 2
+#define _DMA_DEV_INTERF_MAX_BURST_IDX 3
+#define _DMA_DEV_INTERF_CHK_ADDR_ALIGN 4
+
+/* constants */
+#define hrt_dma_v1_zero_extension _DMA_ZERO_EXTEND
+#define hrt_dma_v1_sign_extension _DMA_SIGN_EXTEND
+#define hrt_dma_v1_reverse_elements _DMA_REVERSE_ELEMS
+#define hrt_dma_v1_keep_element_order _DMA_KEEP_ELEM_ORDER
+
+/* Construct address from field type */
+#define _hrt_dma_v1_sel_comp(comp) \
+ (((comp) & _hrt_ones(_DMA_ADDR_SEL_COMP_BITS)) << \
+ _DMA_ADDR_SEL_COMP_IDX)
+#define _hrt_dma_v1_sel_ch(ch) \
+ (((ch) & _hrt_ones(_DMA_ADDR_SEL_CH_REG_BITS)) << \
+ _DMA_ADDR_SEL_CH_REG_IDX)
+#define _hrt_dma_v1_sel_param(param) \
+ (((param) & _hrt_ones(_DMA_ADDR_SEL_PARAM_BITS)) << \
+ _DMA_ADDR_SEL_PARAM_IDX)
+#define _hrt_dma_v1_sel_cg_info(info) \
+ (((info) & _hrt_ones(_DMA_ADDR_SEL_GROUP_COMP_INFO_BITS)) << \
+ _DMA_ADDR_SEL_GROUP_COMP_INFO_IDX)
+#define _hrt_dma_v1_sel_cg_comp(comp) \
+ (((comp) & _hrt_ones(_DMA_ADDR_SEL_GROUP_COMP_BITS)) << \
+ _DMA_ADDR_SEL_GROUP_COMP_IDX)
+#define _hrt_dma_v1_sel_cg_id(gr) \
+ (((gr) & _hrt_ones(_DMA_ADDR_SEL_GROUP_BITS)) << \
+ _DMA_ADDR_SEL_GROUP_IDX)
+#define _hrt_dma_v1_sel_dev_info(info) \
+ (((info) & _hrt_ones(_DMA_ADDR_SEL_DEV_INTERF_INFO_BITS)) << \
+ _DMA_ADDR_SEL_DEV_INTERF_INFO_IDX)
+#define _hrt_dma_v1_sel_dev_id(dev) \
+ (((dev) & _hrt_ones(_DMA_ADDR_SEL_DEV_INTERF_IDX_BITS)) << \
+ _DMA_ADDR_SEL_DEV_INTERF_IDX_IDX)
+
+/* Retrieve return values from packed fields */
+#define _hrt_dma_v1_get_connection(val) \
+ _hrt_get_bits(val, _DMA_CONNECTION_IDX, _DMA_CONNECTION_BITS)
+#define _hrt_dma_v1_get_extension(val) \
+ _hrt_get_bits(val, _DMA_EXTENSION_IDX, _DMA_EXTENSION_BITS)
+#define _hrt_dma_v1_get_element_order(val) \
+ _hrt_get_bits(val, _DMA_ELEM_ORDER_IDX, _DMA_ELEM_ORDER_BITS)
+#define _hrt_dma_v1_get_elements(val) \
+ _hrt_get_bits(val, _DMA_ELEMENTS_IDX, _DMA_ELEMENTS_BITS)
+#define _hrt_dma_v1_get_cropping(val) \
+ _hrt_get_bits(val, _DMA_LEFT_CROPPING_IDX, _DMA_LEFT_CROPPING_BITS)
+
+#define hrt_dma_v1_command_fsm_register_address \
+ _hrt_dma_v1_sel_comp(_DMA_SEL_FSM_CMD)
+#define hrt_dma_v1_channel_parameter_register_address(ch, param) \
+ (_hrt_dma_v1_sel_comp(_DMA_SEL_CH_REG) | _hrt_dma_v1_sel_ch(ch) | \
+ _hrt_dma_v1_sel_param(param))
+#define hrt_dma_v1_conn_group_info_register_address(info_id, comp_id, gr_id) \
+ (_hrt_dma_v1_sel_comp(_DMA_SEL_CONN_GROUP) | \
+ _hrt_dma_v1_sel_cg_info(info_id) | \
+ _hrt_dma_v1_sel_cg_comp(comp_id) | \
+ _hrt_dma_v1_sel_cg_id(gr_id))
+#define hrt_dma_v1_device_interface_info_register_address(info_id, dev_id) \
+ (_hrt_dma_v1_sel_comp(_DMA_SEL_DEV_INTERF) | \
+ _hrt_dma_v1_sel_dev_info(info_id) | \
+ _hrt_dma_v1_sel_dev_id(dev_id))
+#define hrt_dma_v1_reset_register_address \
+ _hrt_dma_v1_sel_comp(_DMA_SEL_RESET)
+
+#endif /* _dma_v1_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/embed.h b/drivers/media/video/atomisp/include/css_hrt/embed.h
new file mode 100644
index 0000000..3ae2997
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/embed.h
@@ -0,0 +1,42 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HRT_EMBED_H_
+#define _HRT_EMBED_H_
+
+#define _hrt_cell_dummy_use_blob(prog) \
+ HRTCAT(_hrt_dummy_use_blob_, prog)()
+#define _hrt_program_transfer_func(prog) \
+ HRTCAT(_hrt_transfer_embedded_, prog)
+#ifdef USE_DYNAMIC_BIN
+#define _hrt_program_blob(prog) \
+ (HRTCAT(_hrt_blob_, prog))
+#else
+#define _hrt_program_blob(prog) \
+ (HRTCAT(_hrt_blob_, prog).data)
+#endif
+#define hrt_embedded_program_size(prog) \
+ HRTCAT(_hrt_size_of_, prog)
+#define hrt_embedded_program_text_size(prog) \
+ HRTCAT(_hrt_text_size_of_, prog)
+
+#endif /* _HRT_EMBED_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/gdc_defs.h b/drivers/media/video/atomisp/include/css_hrt/gdc_defs.h
new file mode 100644
index 0000000..b4b5b2a
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/gdc_defs.h
@@ -0,0 +1,98 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _GDC_DEFS_H_
+#define _GDC_DEFS_H_
+
+/* This file contains the settings for both the gdc (64-way fixed)
+ and the gdc_param (variable nway) devices. */
+
+#define HRT_GDC_N_BITS 6
+#define HRT_GDC_N 64
+
+/* GDC lookup tables entries are 10 bits values, but they're
+ stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
+ A GDC lookup table contains 64 * 4 elements */
+#define HRT_GDC_LUT_BYTES ((HRT_GDC_N * 4) * 2)
+
+#define HRT_GDC_BLI_COEF_BITS 5
+#define HRT_GDC_BLI_COEF_SHIFT (HRT_GDC_BLI_COEF_BITS - 1)
+#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_COEF_SHIFT)
+
+#define HRT_GDC_BCI_COEF_BITS 10
+#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
+#define HRT_GDC_BCI_COEF_SHIFT (HRT_GDC_BCI_COEF_BITS - 2)
+#define HRT_GDC_BCI_COEF_ONE (1 << HRT_GDC_BCI_COEF_SHIFT)
+
+#define HRT_GDC_GDCAC_BITS (6 + 4)
+#define HRT_GDC_GDCAC_ONE (1 << (HRT_GDC_GDCAC_BITS-1))
+
+#define HRT_GDC_COORD_FRAC_BITS 4
+#define HRT_GDC_COORD_ONE (1 << HRT_GDC_COORD_FRAC_BITS)
+
+#define HRT_GDC_MAX_GDC_IPY_16NWAY (15*HRT_GDC_COORD_ONE - 1)
+#define HRT_GDC_MAX_GDC_IPY_64NWAY (49*HRT_GDC_COORD_ONE - 1)
+
+#define _HRT_GDC_REG_ALIGN 4
+
+#define HRT_GDC_NND_CMD 4
+#define HRT_GDC_BLI_CMD 5
+#define HRT_GDC_BCI_CMD 6
+#define HRT_GDC_GD_CAC_CMD 7
+#define HRT_GDC_CONFIG_CMD 8
+
+/* This is how commands are packed into one fifo token */
+#define HRT_GDC_CMD_DATA_POS 16
+#define HRT_GDC_CMD_DATA_BITS 16
+#define HRT_GDC_CMD_BITS 4
+#define HRT_GDC_REG_ID_BITS 8
+#define HRT_GDC_CRUN_BIT (HRT_GDC_CMD_BITS + HRT_GDC_REG_ID_BITS)
+
+#define HRT_GDC_MODE_IDX 0
+#define HRT_GDC_BPP_IDX 1
+#define HRT_GDC_END_IDX 2
+#define HRT_GDC_WOIX_IDX 3
+#define HRT_GDC_WOIY_IDX 4
+#define HRT_GDC_STX_IDX 5
+#define HRT_GDC_STY_IDX 6
+#define HRT_GDC_OXDIM_IDX 7
+#define HRT_GDC_OYDIM_IDX 8
+#define HRT_GDC_SRC_ADDR_IDX 9
+#define HRT_GDC_SRC_END_ADDR_IDX 10
+#define HRT_GDC_SRC_WRAP_ADDR_IDX 11
+#define HRT_GDC_SRC_STRIDE_IDX 12
+#define HRT_GDC_DST_ADDR_IDX 13
+#define HRT_GDC_DST_STRIDE_IDX 14
+#define HRT_GDC_DX_IDX 15
+#define HRT_GDC_DY_IDX 16
+#define HRT_GDC_P0X_IDX 17
+#define HRT_GDC_P1X_IDX 18
+#define HRT_GDC_P2X_IDX 19
+#define HRT_GDC_P3X_IDX 20
+#define HRT_GDC_P0Y_IDX 21
+#define HRT_GDC_P1Y_IDX 22
+#define HRT_GDC_P2Y_IDX 23
+#define HRT_GDC_P3Y_IDX 24
+#define HRT_GDC_SOFT_RST_IDX 25
+#define HRT_GDC_LUT_IDX 32
+
+#endif /* _GDC_DEFS_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/gp_regs_defs.h b/drivers/media/video/atomisp/include/css_hrt/gp_regs_defs.h
new file mode 100644
index 0000000..1d60712
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/gp_regs_defs.h
@@ -0,0 +1,29 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _gp_regs_defs_h
+#define _gp_regs_defs_h
+
+#define _HRT_GP_REGS_IS_FWD_REG_IDX 0
+#define _HRT_GP_REGS_REG_ALIGN 4
+
+#endif /* _gp_regs_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_custom_host_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_custom_host_hrt.h
new file mode 100644
index 0000000..39dc91b
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_custom_host_hrt.h
@@ -0,0 +1,90 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_custom_host_hrt_h_
+#define _hive_isp_css_custom_host_hrt_h_
+
+#include "mfldisp_mem.h"
+
+#define _hrt_master_port_store_8(address, data) \
+ mfld_write_bits_8((unsigned int)(address), ((char)(data)))
+
+#define _hrt_master_port_store_16(address, data) \
+ mfld_write_bits_16((unsigned int)(address), ((short)data))
+
+#define _hrt_master_port_store_32(address, data) \
+ mfld_write_bits_32((unsigned int)(address), ((int)(data)))
+
+#define _hrt_master_port_load_8(address) \
+ mfld_read_bits_8((unsigned int)(address))
+
+#define _hrt_master_port_uload_8(address) \
+ mfld_read_bits_u8((unsigned int)(address))
+
+#define _hrt_master_port_load_16(address) \
+ mfld_read_bits_16((unsigned int)(address))
+
+#define _hrt_master_port_uload_16(address) \
+ mfld_read_bits_u16((unsigned int)(address))
+
+#define _hrt_master_port_load_32(address) \
+ mfld_read_bits_32((unsigned int)(address))
+
+#define _hrt_master_port_uload_32(address) \
+ mfld_read_bits_u32((unsigned int)(address))
+
+#define _hrt_master_port_store_8_volatile(address, data) \
+ mfld_write_bits_8_volatile((unsigned int)(address), \
+ ((char)(data)))
+#define _hrt_master_port_load_8_volatile(address) \
+ mfld_read_bits_8_volatile((unsigned int)(address))
+
+#define _hrt_master_port_uload_8_volatile(address) \
+ mfld_read_bits_u8_volatile((unsigned int)(address))
+
+#define _hrt_master_port_store_16_volatile(address, data) \
+ mfld_write_bits_16_volatile((unsigned int)(address),\
+ ((short)(data)))
+
+#define _hrt_master_port_load_16_volatile(address) \
+ mfld_read_bits_16_volatile((unsigned int)(address))
+
+#define _hrt_master_port_uload_16_volatile(address) \
+ mfld_read_bits_u16_volatile((unsigned int)(address))
+
+#define _hrt_master_port_store_32_volatile(address, data) \
+ mfld_write_bits_32_volatile((unsigned int)(address), \
+ ((int)(data)))
+
+#define _hrt_master_port_load_32_volatile(address) \
+ mfld_read_bits_32_volatile((unsigned int)(address))
+
+#define _hrt_master_port_uload_32_volatile(address) \
+ mfld_read_bits_u32_volatile((unsigned int)(address))
+
+static inline void
+hrt_sleep(void)
+{
+ udelay(1);
+}
+
+#endif /* _hive_isp_css_custom_host_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.c b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.c
new file mode 100644
index 0000000..c4a7364
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.c
@@ -0,0 +1,358 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <hrt/vector.h>
+#ifdef HRT_CSIM
+#include <hrt/error.h>
+#endif
+#include "hive_isp_css_defs.h"
+#include "hive_isp_css_ddr_hrt.h"
+#include "hive_isp_css_mm_hrt.h"
+
+#define BYTES_PER_XWORD (HIVE_ISP_DDR_WORD_BITS/8)
+#define ceil_div(a, b) (((a)+(b)-1)/(b))
+
+struct dma_spec_t {
+ unsigned int num_elems;
+ unsigned int elem_bits;
+};
+
+static struct dma_spec_t specs[] = HIVE_ISP_DDR_DMA_SPECS;
+static unsigned int num_specs = sizeof(specs) / sizeof(*specs);
+
+static unsigned int
+dma_num_elems_to_elem_width(unsigned int num_elems, unsigned int *bits)
+{
+ unsigned int i;
+ for (i = 0; i < num_specs; i++) {
+ if (specs[i].num_elems == num_elems) {
+ *bits = specs[i].elem_bits;
+ return 1;
+ }
+ }
+#ifdef HRT_CSIM
+ hrt_warning("cannot translate number of elements (%d)"
+ " to element bits in dma", num_elems);
+#endif
+ return 0;
+}
+
+static unsigned int
+dma_elem_width_to_num_elems(unsigned int bits, unsigned int *num_elems)
+{
+ unsigned int i;
+ for (i = 0; i < num_specs; i++) {
+ if (specs[i].elem_bits == bits) {
+ *num_elems = specs[i].num_elems;
+ return 1;
+ }
+ }
+#ifdef HRT_CSIM
+ hrt_warning("cannot translate element width (%d)"
+ " to number of elements per word", num_elems);
+#endif
+ return 0;
+}
+
+unsigned int
+hrt_isp_css_stride_of_image_in_ddr(unsigned int width,
+ unsigned int bits_per_element)
+{
+ unsigned int elems_per_xword, xwords_per_line;
+
+ if (dma_elem_width_to_num_elems(bits_per_element, &elems_per_xword) ==
+ 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+ return xwords_per_line * BYTES_PER_XWORD;
+}
+
+unsigned int
+hrt_isp_css_sizeof_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ return hrt_isp_css_stride_of_image_in_ddr(width,
+ bits_per_element) * height;
+}
+
+void *
+hrt_isp_css_alloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_alloc(bytes);
+}
+
+void *
+hrt_isp_css_calloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_calloc(bytes);
+}
+
+unsigned int
+hrt_isp_css_read_image_from_ddr(unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend,
+ void *virt_addr)
+{
+ unsigned int i, j, k, elem_bits, xwords_per_line;
+ char xword_buf[BYTES_PER_XWORD];
+ /* this is the maximum number of elements in an xword */
+ int elem_buf[BYTES_PER_XWORD];
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return 0;
+ if (elem_bits == 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+
+ for (i = 0; i < height; i++) {
+ unsigned int elems_in_line = width;
+ for (j = 0; j < xwords_per_line; j++) {
+ unsigned int elems_in_word = elems_per_xword;
+ if (elems_in_word > elems_in_line)
+ elems_in_word = elems_in_line;
+ hrt_isp_css_mm_load(virt_addr, xword_buf,
+ BYTES_PER_XWORD);
+ _hrt_decode_vector(xword_buf, elem_buf, elem_bits,
+ elem_bits, elems_per_xword,
+ sign_extend);
+ for (k = 0; k < elems_in_word;
+ k++, elems_in_line--, img_buf++)
+ *img_buf = (unsigned short) elem_buf[k];
+ virt_addr += BYTES_PER_XWORD;
+ }
+ }
+
+ return 1;
+}
+
+unsigned int
+hrt_isp_css_write_image_to_ddr(const unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend,
+ void *virt_addr)
+{
+ unsigned int i, j, k, elem_bits, xwords_per_line;
+ char xword_buf[BYTES_PER_XWORD];
+ int elem_buf[BYTES_PER_XWORD];
+
+ if (!dma_num_elems_to_elem_width(elems_per_xword, &elem_bits))
+ return 0;
+ if (elem_bits == 0)
+ return 0;
+ xwords_per_line = ceil_div(width, elems_per_xword);
+
+ for (i = 0; i < height; i++) {
+ unsigned int elems_in_line = width;
+ for (j = 0; j < xwords_per_line; j++) {
+ unsigned int elems_in_word = elems_per_xword;
+ if (elems_in_word > elems_in_line)
+ elems_in_word = elems_in_line;
+ for (k = 0; k < elems_in_word;
+ k++, elems_in_line--, img_buf++)
+ elem_buf[k] = *img_buf;
+ _hrt_encode_vector(elem_buf, xword_buf, elem_bits,
+ elem_bits, elems_per_xword,
+ sign_extend);
+ hrt_isp_css_mm_store(virt_addr, xword_buf,
+ BYTES_PER_XWORD);
+ virt_addr += BYTES_PER_XWORD;
+ }
+ }
+
+ return 1;
+}
+
+void *
+hrt_isp_css_alloc_gdc_lut_in_ddr(void)
+{
+ return hrt_isp_css_mm_alloc(HRT_GDC_LUT_BYTES);
+}
+
+void
+hrt_isp_css_write_gdc_lut_to_ddr(short lut[4][HRT_GDC_N], void *virt_addr)
+{
+ unsigned int i;
+ for (i = 0; i < HRT_GDC_N; i++) {
+ unsigned int entry_0 = lut[0][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_1 = lut[1][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_2 = lut[2][i] & HRT_GDC_BCI_COEF_MASK,
+ entry_3 = lut[3][i] & HRT_GDC_BCI_COEF_MASK,
+ word_0 = entry_0 | (entry_1 << HRT_GDC_BCI_COEF_BITS),
+ word_1 = entry_2 | (entry_3 << HRT_GDC_BCI_COEF_BITS);
+ hrt_isp_css_mm_store_int(virt_addr, word_0);
+ virt_addr += 4;
+ hrt_isp_css_mm_store_int(virt_addr, word_1);
+ virt_addr += 4;
+ }
+}
+
+#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM
+void *
+hrt_isp_css_alloc_image_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (dma_num_elems_to_elem_width(elems_per_xword, &elem_bits) == 0)
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_alloc_contiguous(bytes);
+}
+
+void *
+hrt_isp_css_calloc_image_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword)
+{
+ unsigned int elem_bits;
+ size_t bytes;
+
+ if (dma_num_elems_to_elem_width(elems_per_xword, &elem_bits) == 0)
+ return NULL;
+ bytes = hrt_isp_css_sizeof_image_in_ddr(width, height, elem_bits);
+ return hrt_isp_css_mm_calloc_contiguous(bytes);
+}
+
+void *
+hrt_isp_css_alloc_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ size_t bytes;
+ bytes =
+ hrt_isp_css_sizeof_image_in_ddr(width, height, bits_per_element);
+ return hrt_isp_css_mm_alloc_contiguous(bytes);
+}
+#endif
+
+unsigned int
+hrt_isp_css_read_unsigned(unsigned short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(source_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_read_image_from_ddr(target, width, height,
+ elems_per_xword, 0, source);
+}
+
+unsigned int
+hrt_isp_css_read_signed(short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(source_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_read_image_from_ddr((unsigned short *) target, width,
+ height, elems_per_xword, 1,
+ source);
+}
+
+unsigned int
+hrt_isp_css_write_unsigned(const unsigned short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(target_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_write_image_to_ddr(source, width, height,
+ elems_per_xword, 0, target);
+}
+
+unsigned int
+hrt_isp_css_write_signed(const short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target)
+{
+ unsigned int elems_per_xword;
+
+ if (dma_elem_width_to_num_elems(target_bits_per_element,
+ &elems_per_xword) == 0)
+ return 0;
+ return hrt_isp_css_write_image_to_ddr((const unsigned short *) source,
+ width, height, elems_per_xword, 1,
+ target);
+}
+
+void *
+hrt_isp_css_alloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ size_t bytes;
+
+ bytes =
+ hrt_isp_css_sizeof_image_in_ddr(width, height, bits_per_element);
+ return hrt_isp_css_mm_alloc(bytes);
+}
+
+void *
+hrt_isp_css_calloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element)
+{
+ size_t bytes;
+
+ bytes =
+ hrt_isp_css_sizeof_image_in_ddr(width, height, bits_per_element);
+ return hrt_isp_css_mm_calloc(bytes);
+}
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.h
new file mode 100644
index 0000000..94f7502
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_ddr_hrt.h
@@ -0,0 +1,143 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_dma_hrt_h_
+#define _hive_isp_css_dma_hrt_h_
+
+#include <hmm/hmm.h>
+#include <gdc_defs.h>
+
+/* This function reads an image from DDR and stores it in the img_buf array
+ * that has been allocated by the caller.
+ * The specifics of how the pixels are stored into DDR by the DMA are taken
+ * into account (bits padded to a width of 256, depending on the number of
+ * elements per ddr word).
+ * The DMA specific parameters give to this function (elems_per_xword and
+ * sign_extend) should correspond to those given to the DMA engine.
+ * The address is a virtual address which will be translated to a physical
+ * address before data is loaded from or stored to that address.
+ *
+ * The return value is 0 in case of success and 1 in case of failure.
+ */
+unsigned int
+hrt_isp_css_read_image_from_ddr(unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend, void *virt_addr);
+
+/* This function writes an image to DDR, keeping the same aspects into
+ account as the read_image function above. */
+unsigned int
+hrt_isp_css_write_image_to_ddr(const unsigned short *img_buf,
+ unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword,
+ unsigned int sign_extend,
+ void *virt_addr);
+
+/* return the size in bytes of an image (frame or plane). */
+unsigned int
+hrt_isp_css_sizeof_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element);
+
+unsigned int
+hrt_isp_css_stride_of_image_in_ddr(unsigned int width,
+ unsigned int bits_per_element);
+
+void *
+hrt_isp_css_alloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword);
+
+void *
+hrt_isp_css_calloc_image_in_ddr(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword);
+
+void *hrt_isp_css_alloc_gdc_lut_in_ddr(void);
+
+void
+hrt_isp_css_write_gdc_lut_to_ddr(short values[4][HRT_GDC_N],
+ void *virt_addr);
+
+#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM
+void *
+hrt_isp_css_alloc_image_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword);
+
+void *
+hrt_isp_css_calloc_image_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int elems_per_xword);
+
+void *
+hrt_isp_css_alloc_for_display(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element);
+#endif
+
+/* New set of functions, these do not require the elems_per_xword,
+ * but use bits_per_element instead, this way the user does not need to
+ * know about the width of a DDR word.
+ */
+unsigned int
+hrt_isp_css_read_unsigned(unsigned short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source);
+
+unsigned int
+hrt_isp_css_read_signed(short *target,
+ unsigned int width,
+ unsigned int height,
+ unsigned int source_bits_per_element,
+ void *source);
+
+unsigned int
+hrt_isp_css_write_unsigned(const unsigned short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target);
+
+unsigned int
+hrt_isp_css_write_signed(const short *source,
+ unsigned int width,
+ unsigned int height,
+ unsigned int target_bits_per_element,
+ void *target);
+
+void *
+hrt_isp_css_alloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element);
+
+void *
+hrt_isp_css_calloc(unsigned int width,
+ unsigned int height,
+ unsigned int bits_per_element);
+
+#endif /* _hive_isp_css_dma_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_defs.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_defs.h
new file mode 100644
index 0000000..700a41a
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_defs.h
@@ -0,0 +1,196 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_defs_h
+#define _hive_isp_css_defs_h
+
+#define HIVE_ISP_CTRL_DATA_WIDTH 32
+#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32
+#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1
+#define HIVE_ISP_NUM_GPIO_PINS 10
+
+/* This list of vector num_elems/elem_bits pairs is valid both
+ in C as initializer and in the DMA parameter list */
+#define HIVE_ISP_DDR_DMA_SPECS { {32, 8}, {16, 16}, {18, 14}, \
+ {25, 10}, {21, 12} }
+#define HIVE_ISP_DDR_WORD_BITS 256
+#define HIVE_ISP_DDR_BYTES (256 * 1024 * 1024)
+#define HIVE_ISP_PAGE_SHIFT 12
+#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
+
+/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value,
+ * the wide bus just before the DDRAM gets an extra dummy port where
+ * address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto.
+ * This effectively creates an offset for the DDRAM from system perspective.
+ */
+#define HIVE_ISP_DDR_BASE_OFFSET 0 /* 0x200000 */
+
+#define HIVE_DMA_ISP_BUS_CONN 0
+#define HIVE_DMA_ISP_DDR_CONN 1
+#define HIVE_DMA_BUS_DDR_CONN 2
+#define HIVE_DMA_ISP_MASTER master_port0
+#define HIVE_DMA_BUS_MASTER master_port1
+#define HIVE_DMA_DDR_MASTER master_port2
+#define HIVE_DMA_NUM_CHANNELS 8
+
+#define HIVE_IF_PIXEL_WIDTH 12
+
+#define HIVE_MMU_TLB_SETS 16
+#define HIVE_MMU_TLB_SET_BLOCKS 8
+#define HIVE_MMU_TLB_BLOCK_ELEMENTS 8
+#define HIVE_MMU_PAGE_TABLE_LEVELS 2
+#define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE
+
+#define HIVE_ISP_CH_ID_BITS 2
+#define HIVE_ISP_FMT_TYPE_BITS 5
+#define HIVE_ISP_ISEL_SEL_BITS 2
+
+/* gp_register register id's */
+#define HIVE_GP_REGS_SWITCH_IF_IDX 0
+#define HIVE_GP_REGS_SWITCH_DMA_IDX 1
+#define HIVE_GP_REGS_SWITCH_GDC_IDX 2
+
+#define HIVE_GP_REGS_SYNCGEN_ENABLE_IDX 3
+#define HIVE_GP_REGS_SYNCGEN_NR_PIX_IDX 4
+#define HIVE_GP_REGS_SYNCGEN_NR_LINES_IDX 5
+#define HIVE_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
+#define HIVE_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
+
+#define HIVE_GP_REGS_ISEL_SOF_IDX 8
+#define HIVE_GP_REGS_ISEL_EOF_IDX 9
+#define HIVE_GP_REGS_ISEL_SOL_IDX 10
+#define HIVE_GP_REGS_ISEL_EOL_IDX 11
+
+#define HIVE_GP_REGS_PRBS_ENABLE 12
+#define HIVE_GP_REGS_PRBS_ENABLE_PORT_B 13
+#define HIVE_GP_REGS_PRBS_LFSR_RESET_VALUE 14
+
+#define HIVE_GP_REGS_TPG_ENABLE 15
+#define HIVE_GP_REGS_TPG_ENABLE_PORT_B 16
+#define HIVE_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
+#define HIVE_GP_REGS_TPG_VER_CNT_MASK_IDX 18
+#define HIVE_GP_REGS_TPG_XY_CNT_MASK_IDX 19
+#define HIVE_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
+#define HIVE_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
+
+#define HIVE_GP_REGS_ISEL_CH_ID_IDX 22
+#define HIVE_GP_REGS_ISEL_FMT_TYPE_IDX 23
+#define HIVE_GP_REGS_ISEL_DATA_SEL_IDX 24
+#define HIVE_GP_REGS_ISEL_SBAND_SEL_IDX 25
+#define HIVE_GP_REGS_ISEL_SYNC_SEL_IDX 26
+
+/* HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_? have to be sequential ! */
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_0 27
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_1 28
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_2 29
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_3 30
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_4 31
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_5 32
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_6 33
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_7 34
+
+#define HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_BASE \
+ HIVE_GP_REGS_INPUT_SWITCH_LUT_REG_0
+#define HIVE_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 35
+
+#define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 36
+#define HIVE_GP_REGS_IDLE_IDX 37
+#define HIVE_GP_REGS_IRQ_IDX 38
+
+#define HIVE_GP_REGS_MIPI_FIFO_FULL 39
+#define HIVE_GP_REGS_MIPI_USED_DWORD 40
+
+#define HIVE_GP_REGS_SP_STREAM_STAT 41
+#define HIVE_GP_REGS_MOD_STREAM_STAT 42
+#define HIVE_GP_REGS_ISP_STREAM_STAT 43
+
+#define HIVE_GP_REGS_CH_ID_FMT_TYPE_IDX 44
+
+/* order of the input bits for the irq controller */
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_0_BIT_ID 0
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_1_BIT_ID 1
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_2_BIT_ID 2
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_3_BIT_ID 3
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_4_BIT_ID 4
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_5_BIT_ID 5
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_6_BIT_ID 6
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_7_BIT_ID 7
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_8_BIT_ID 8
+#define HIVE_TESTBENCH_IRQ_SOURCE_GPIO_PIN_9_BIT_ID 9
+#define HIVE_TESTBENCH_IRQ_SOURCE_SP_BIT_ID 10
+#define HIVE_TESTBENCH_IRQ_SOURCE_ISP_BIT_ID 11
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_BIT_ID 12
+#define HIVE_TESTBENCH_IRQ_SOURCE_PRIM_IF_BIT_ID 13
+#define HIVE_TESTBENCH_IRQ_SOURCE_PRIM_B_IF_BIT_ID 14
+#define HIVE_TESTBENCH_IRQ_SOURCE_SEC_IF_BIT_ID 15
+#define HIVE_TESTBENCH_IRQ_SOURCE_MEM_COPY_BIT_ID 16
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_FIFO_FULL_BIT_ID 17
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_SOF_BIT_ID 18
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_EOF_BIT_ID 19
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_SOL_BIT_ID 20
+#define HIVE_TESTBENCH_IRQ_SOURCE_MIPI_EOL_BIT_ID 21
+#define HIVE_TESTBENCH_IRQ_SOURCE_SYNC_GEN_SOF_BIT_ID 22
+#define HIVE_TESTBENCH_IRQ_SOURCE_SYNC_GEN_EOF_BIT_ID 23
+#define HIVE_TESTBENCH_IRQ_SOURCE_SYNC_GEN_SOL_BIT_ID 24
+#define HIVE_TESTBENCH_IRQ_SOURCE_SYNC_GEN_EOL_BIT_ID 25
+#define HIVE_TESTBENCH_IRQ_SOURCE_CSS_GEN_SHORT_VALID_BIT_ID 26
+#define HIVE_TESTBENCH_IRQ_SOURCE_CSS_GEN_SHORT_ACCEPT_BIT_ID 27
+#define HIVE_TESTBENCH_IRQ_SOURCE_SIDEBAND_CHANGED_BIT_ID 28
+
+#define HIVE_TESTBENCH_IRQ_SOURCE_SW_PIN_0_BIT_ID 29
+#define HIVE_TESTBENCH_IRQ_SOURCE_SW_PIN_1_BIT_ID 30
+#define HIVE_TESTBENCH_IRQ_SOURCE_SW_PIN_2_BIT_ID 31
+
+#define HIVE_ISP_NUM_USED_IRQ_INPUTS \
+ (HIVE_TESTBENCH_IRQ_SOURCE_SW_PIN_0_BIT_ID - \
+ HIVE_TESTBENCH_IRQ_SOURCE_SP_BIT_ID)
+
+#define HIVE_GP_REGS_IRQ_REG_WIDTH \
+ (HIVE_ISP_CTRL_DATA_WIDTH - \
+ HIVE_TESTBENCH_IRQ_SOURCE_SW_PIN_0_BIT_ID)
+
+/* testbench signals: */
+
+/* GP adapter register ids */
+#define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0
+#define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1
+#define HIVE_TESTBENCH_IRQ_REG_IDX 2
+#define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3
+#define HIVE_TESTBENCH_IDLE_REG_IDX 4
+#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
+
+/* Signal monitor input bit ids */
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_O_BIT_ID 0
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_1_BIT_ID 1
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_2_BIT_ID 2
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_3_BIT_ID 3
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_4_BIT_ID 4
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_5_BIT_ID 5
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_6_BIT_ID 6
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_7_BIT_ID 7
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_8_BIT_ID 8
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_GPIO_PIN_9_BIT_ID 9
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_IRQ_PIN_BIT_ID 10
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_SDRAM_WAKEUP_PIN_BIT_ID 11
+#define HIVE_TESTBENCH_SIG_MON_SOURCE_IDLE_PIN_BIT_ID 12
+
+#endif /* _hive_isp_css_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_host_ids_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_host_ids_hrt.h
new file mode 100644
index 0000000..17be407
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_host_ids_hrt.h
@@ -0,0 +1,66 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_host_ids_hrt_h_
+#define _hive_isp_css_host_ids_hrt_h_
+
+/* ISP_CSS identifiers */
+#define ISP testbench_isp_isp
+#define SP testbench_isp_scp
+#define IF_PRIM testbench_isp_ift_prim
+#define IF_PRIM_B testbench_isp_ift_prim_b
+#define IF_SEC testbench_isp_ift_sec
+#define STR_TO_MEM testbench_isp_mem_cpy
+#define CSS_RECEIVER testbench_isp_css_receiver
+#define TC testbench_isp_gpd_tc
+#define DMA testbench_isp_isp_dma
+#define GDC testbench_isp_gdc
+#define IRQ_CTRL testbench_isp_gpd_irq_ctrl
+#define GPIO testbench_isp_gpd_c_gpio
+#define GP_REGS testbench_isp_gpd_gp_reg
+#define MMU testbench_isp_c_mmu
+#define ISEL_FA testbench_isp_gpd_fa_isel
+/* next is actually not FIFO but FIFO adapter, or slave to streaming adapter */
+#define ISP_SP_FIFO testbench_isp_gpd_fa_sp_isp
+#define GP_FIFO testbench_isp_gpd_sf_2isel_in
+#define FIFO_GPF_ISEL testbench_isp_gpd_sf_2isel_in
+#define FIFO_GPF_SP testbench_isp_gpd_sf_gpf2sp_in
+#define FIFO_GPF_ISP testbench_isp_gpd_sf_gpf2isp_in
+#define FIFO_SP_GPF testbench_isp_gpd_sf_sp2gpf_in
+#define FIFO_ISP_GPF testbench_isp_gpd_sf_isp2gpf_in
+#define OCP_MASTER testbench_isp_cio2ocp_wide_data_out_mt
+#define IF_SEC_MASTER testbench_isp_ift_sec_mt_out
+#define SP_IN_FIFO testbench_isp_gpd_sf_gpf2sp_in
+#define SP_OUT_FIFO testbench_isp_gpd_sf_sp2gpf_out
+#define ISP_IN_FIFO testbench_isp_gpd_sf_gpf2isp_in
+#define ISP_OUT_FIFO testbench_isp_gpd_sf_isp2gpf_out
+#define GEN_SHORT_PACK_PORT testbench_isp_ModStrMon_out10
+
+/* Testbench identifiers */
+#define DDR testbench_ddram
+#define XMEM DDR
+#define GPIO_ADAPTER testbench_gp_adapter
+#define SIG_MONITOR testbench_sig_mon
+#define DDR_SLAVE testbench_ddram_ip0
+#define HOST_MASTER host_op0
+
+#endif /* _hive_isp_css_host_ids_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_if_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_if_hrt.h
new file mode 100644
index 0000000..ce08dbc
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_if_hrt.h
@@ -0,0 +1,42 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HIVE_ISP_CSS_IF_HRT_H_
+#define _HIVE_ISP_CSS_IF_HRT_H_
+
+#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM
+#define dev_sys_isp_clus_ift_prim_vector_alignment ISP_VEC_ALIGN
+#define dev_sys_isp_clus_ift_prim_b_vector_alignment ISP_VEC_ALIGN
+#define dev_sys_isp_clus_ift_sec_vector_alignment \
+ (dev_sys_isp_clus_ift_sec_mt_out_data_width / 8)
+#define dev_sys_isp_clus_mem_cpy_vector_alignment \
+ (dev_sys_isp_clus_mem_cpy_mt_out_data_width / 8)
+#else
+#define testbench_isp_ift_prim_vector_alignment ISP_VEC_ALIGN
+#define testbench_isp_ift_prim_b_vector_alignment ISP_VEC_ALIGN
+#define testbench_isp_ift_sec_vector_alignment \
+ (testbench_isp_ift_sec_mt_out_data_width / 8)
+#define testbench_isp_mem_cpy_vector_alignment \
+ (testbench_isp_mem_cpy_mt_out_data_width / 8)
+#endif
+
+#endif /* _HIVE_ISP_CSS_IF_HRT_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_irq_types_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_irq_types_hrt.h
new file mode 100644
index 0000000..fb7b4c8
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_irq_types_hrt.h
@@ -0,0 +1,77 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_
+#define _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_
+
+/* these are the indices of each interrupt in the
+ * interrupt controller's registers. these can be used
+ * as the irq_id argument to the hrt functions irq_controller.h.
+ */
+enum hrt_isp_css_irq {
+ hrt_isp_css_irq_gpio_0,
+ hrt_isp_css_irq_gpio_1,
+ hrt_isp_css_irq_gpio_2,
+ hrt_isp_css_irq_gpio_3,
+ hrt_isp_css_irq_gpio_4,
+ hrt_isp_css_irq_gpio_5,
+ hrt_isp_css_irq_gpio_6,
+ hrt_isp_css_irq_gpio_7,
+ hrt_isp_css_irq_gpio_8,
+ hrt_isp_css_irq_gpio_9,
+ hrt_isp_css_irq_sp,
+ hrt_isp_css_irq_isp,
+ hrt_isp_css_irq_mipi,
+ hrt_isp_css_irq_ift_prim,
+ hrt_isp_css_irq_ift_prim_b,
+ hrt_isp_css_irq_ift_sec,
+ hrt_isp_css_irq_ift_mem_cpy,
+ hrt_isp_css_irq_mipi_fifo_full,
+ hrt_isp_css_irq_mipi_sof,
+ hrt_isp_css_irq_mipi_eof,
+ hrt_isp_css_irq_mipi_sol,
+ hrt_isp_css_irq_mipi_eol,
+ hrt_isp_css_irq_syncgen_sof,
+ hrt_isp_css_irq_syncgen_eof,
+ hrt_isp_css_irq_syncgen_sol,
+ hrt_isp_css_irq_syncgen_eol,
+#ifdef CSS_RECEIVER
+ hrt_isp_css_irq_css_gen_short_0,
+ hrt_isp_css_irq_css_gen_short_1,
+ hrt_isp_css_irq_sideband_changed,
+#endif
+ /* The ASIC system has only 3 SW interrupts, so the FPGA system is limited
+ * by this to 3 as well. */
+ hrt_isp_css_irq_sw_0,
+ hrt_isp_css_irq_sw_1,
+ hrt_isp_css_irq_sw_2,
+/* this must (obviously) be the last on in the enum */
+ hrt_isp_css_irq_num_irqs
+};
+
+enum hrt_isp_css_irq_status {
+ hrt_isp_css_irq_status_error,
+ hrt_isp_css_irq_status_more_irqs,
+ hrt_isp_css_irq_status_success
+};
+
+#endif /* _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.c b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.c
new file mode 100644
index 0000000..4f4dd5d
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.c
@@ -0,0 +1,237 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <string.h>
+#include <hmm/hmm.h>
+
+#include "hive_isp_css_hrt.h"
+#include "hive_isp_css_mm_hrt.h"
+
+#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM
+#define mmu_ddr1_addr() hrt_master_to_slave_address(OCP_MASTER, DDR1_SLAVE)
+#define host_ddr1_addr() hrt_master_to_slave_address(HOST_MASTER, DDR1_SLAVE)
+#define mmu_ddr2_addr() hrt_master_to_slave_address(OCP_MASTER, DDR2_SLAVE)
+#define host_ddr2_addr() hrt_master_to_slave_address(HOST_MASTER, DDR2_SLAVE)
+#else
+#define mmu_addr() hrt_master_to_slave_address(OCP_MASTER, DDR_SLAVE)
+#define host_addr() hrt_master_to_slave_address(HOST_MASTER, DDR_SLAVE)
+#endif
+
+#define BYTES_PER_XWORD (HIVE_ISP_DDR_WORD_BITS/8)
+
+/* we use malloc/free if the custom host is enabled and the
+ * NO_OS is not enabled. When NO_OS is enabled, we're running on the SoC
+ * with no operating system, where malloc returns a physical address, so we
+ * need hmm to do the virtual memory management. */
+#if defined(HRT_HW) && \
+ defined(HRT_ISP_CSS_CUSTOM_HOST) && \
+ !defined(HRT_ISP_CSS_NO_OS)
+#define USE_HMM 0
+#else
+#define USE_HMM 1
+#endif
+
+#if USE_HMM
+static unsigned init_done;
+
+static void
+inv_tlb(void)
+{
+ hrt_mmu_invalidate_TLB(MMU);
+}
+
+static void
+hrt_isp_css_mm_init(void)
+{
+ void *mmu_base = NULL;
+
+ /* We initialize the memory manager with the physical memory and enable
+ * the virtual memory system. This gives us the page used for the first
+ * level of pages which is programmed into the MMU. To prevent the DMA
+ * overwriting data that immediately follows target, we make sure every
+ * allocated piece of memory is aligned to the width in bytes of a
+ * system word as seen by the DMA.
+ */
+ hmm_init_virt_mem(HIVE_ISP_PAGE_SHIFT, inv_tlb, BYTES_PER_XWORD);
+#if defined(HRT_CSIM) || defined(HRT_RTL)
+ /* prevent mmu from generating uninitialized
+ * read warnings when fetching a block of L1 or
+ * L2 data. */
+ hmm_init_l_pages(1);
+#endif
+
+#if defined(_HIVE_ISP_CSS_FPGA_SYSTEM)
+ hmm_register_zone(host_ddr1_addr(), mmu_ddr1_addr(),
+ HIVE_ISP_DDR_BYTES);
+ hmm_register_zone(host_ddr2_addr(), mmu_ddr2_addr(),
+ HIVE_ISP_DDR_BYTES);
+#elif defined(HRT_RTL)
+ hmm_register_zone(host_addr(), mmu_addr(), 32 * 1024 * 1024);
+#elif defined(HRT_ISP_CSS_NO_OS)
+ {
+ /* this is the case for the IA SOC with no OS, we allocate a
+ * piece of physical memory and assign that to the hmm library.
+ */
+ unsigned int bytes = 128 * 1024 * 1024; /* 128MB */
+ void *phys_mem = malloc(bytes);
+ hmm_register_zone((unsigned int) phys_mem,
+ (unsigned int) phys_mem, bytes);
+ }
+#else
+ hmm_register_zone(host_addr(), mmu_addr(), HIVE_ISP_DDR_BYTES);
+#endif
+ mmu_base = hmm_l1_page_mmu_address();
+ hrt_mmu_set_page_table_base_address(MMU, (unsigned long) mmu_base);
+ inv_tlb();
+ init_done = 1;
+}
+#endif /* USE_HMM */
+
+void
+hrt_isp_css_mm_load(void *virt_addr, void *data, size_t bytes)
+{
+#if USE_HMM
+ hmm_load(virt_addr, data, bytes);
+#else
+ memcpy(data, (void *) virt_addr, bytes);
+#endif
+}
+
+void
+hrt_isp_css_mm_store(void *virt_addr, const void *data, size_t bytes)
+{
+#if USE_HMM
+ hmm_store(virt_addr, data, bytes);
+#else
+ memcpy((void *) virt_addr, data, bytes);
+#endif
+}
+
+void
+hrt_isp_css_mm_free(void *virt_addr)
+{
+#if USE_HMM
+ hmm_free(virt_addr);
+#else
+ free((void *) virt_addr);
+#endif
+}
+
+void *
+hrt_isp_css_mm_alloc(size_t bytes)
+{
+#if USE_HMM
+ if (!init_done)
+ hrt_isp_css_mm_init();
+ return hmm_alloc(bytes);
+#else
+ return malloc(bytes);
+#endif
+}
+
+void *
+hrt_isp_css_mm_calloc(size_t bytes)
+{
+#if USE_HMM
+ if (!init_done)
+ hrt_isp_css_mm_init();
+ return hmm_calloc(bytes);
+#else
+ return calloc(bytes, 1);
+#endif
+}
+
+int
+hrt_isp_css_mm_load_int(void *virt_addr)
+{
+ int v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+short
+hrt_isp_css_mm_load_short(void *virt_addr)
+{
+ short v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+char
+hrt_isp_css_mm_load_char(void *virt_addr)
+{
+ char v = 0;
+ hrt_isp_css_mm_load(virt_addr, &v, sizeof(v));
+ return v;
+}
+
+void
+hrt_isp_css_mm_store_char(void *virt_addr, char data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void
+hrt_isp_css_mm_store_short(void *virt_addr, short data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void
+hrt_isp_css_mm_store_int(void *virt_addr, int data)
+{
+ hrt_isp_css_mm_store(virt_addr, &data, sizeof(data));
+}
+
+void *
+hrt_isp_css_virt_to_phys(void *virt_addr)
+{
+#if USE_HMM
+ return hmm_virt_to_phys(virt_addr);
+#else
+ return virt_addr;
+#endif
+}
+
+void *
+hrt_isp_css_mm_alloc_contiguous(size_t bytes)
+{
+#if USE_HMM
+ if (!init_done)
+ hrt_isp_css_mm_init();
+ return hmm_alloc_contiguous(bytes);
+#else
+ return malloc(bytes);
+#endif
+}
+
+void *
+hrt_isp_css_mm_calloc_contiguous(size_t bytes)
+{
+#if USE_HMM
+ if (!init_done)
+ hrt_isp_css_mm_init();
+ return hmm_calloc_contiguous(bytes);
+#else
+ return calloc(bytes, 1);
+#endif
+}
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.h
new file mode 100644
index 0000000..5e9d128
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_mm_hrt.h
@@ -0,0 +1,63 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_mm_hrt_h_
+#define _hive_isp_css_mm_hrt_h_
+
+#ifndef HRT_KERNEL
+/* size_t is defined already in kernel mode */
+#include <stdlib.h>
+#endif
+#include <hmm/hmm.h>
+
+/* Allocate memory, returns a virtual address */
+void *hrt_isp_css_mm_alloc(size_t bytes);
+
+/* allocate memory and initialize with zeros,
+ returns a virtual address */
+void *hrt_isp_css_mm_calloc(size_t bytes);
+
+/* Free memory, given a virtual address */
+void hrt_isp_css_mm_free(void *virt_addr);
+
+/* Store data to a virtual address */
+void hrt_isp_css_mm_load(void *virt_addr, void *data, size_t bytes);
+
+/* Load data from a virtual address */
+void hrt_isp_css_mm_store(void *virt_addr, const void *data, size_t bytes);
+
+int hrt_isp_css_mm_load_int(void *virt_addr);
+short hrt_isp_css_mm_load_short(void *virt_addr);
+char hrt_isp_css_mm_load_char(void *virt_addr);
+
+void hrt_isp_css_mm_store_char(void *virt_addr, char data);
+void hrt_isp_css_mm_store_short(void *virt_addr, short data);
+void hrt_isp_css_mm_store_int(void *virt_addr, int data);
+
+/* translate a virtual to a physical address, used to program
+ the display driver on the FPGA system */
+void *hrt_isp_css_virt_to_phys(void *virt_addr);
+
+void *hrt_isp_css_mm_alloc_contiguous(size_t bytes);
+void *hrt_isp_css_mm_calloc_contiguous(size_t bytes);
+
+#endif /* _hive_isp_css_mm_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_program_load_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_program_load_hrt.h
new file mode 100644
index 0000000..78c576c
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_program_load_hrt.h
@@ -0,0 +1,154 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HIVE_ISP_CSS_PROGRAM_LOAD_HRT_H_
+#define _HIVE_ISP_CSS_PROGRAM_LOAD_HRT_H_
+
+#include <defs.h>
+#include <embed.h>
+
+#include "hive_isp_css_mm_hrt.h"
+#ifdef HRT_CSIM
+#include <cell.h>
+#include "hive_isp_css_hrt.h"
+#elif !defined(_sp_var_addr)
+/* Todo: move this to the hrt */
+#define _sp_var_addr(var) HRTCAT(HIVE_ADDR_, var)
+#define _sp_var_size(var) HRTCAT(HIVE_SIZE_, var)
+#endif
+
+#if defined(PALLADIUM_RECORD) || defined(PALLADIUM_PLAYBACK)
+/* ASIC */
+#define testbench_isp_isp_MIN_TEXT_SIZE 0
+#define testbench_isp_scp_MIN_TEXT_SIZE 500000
+/* FPGA */
+#define dev_sys_isp_clus_isp_MIN_TEXT_SIZE 0
+#define dev_sys_isp_clus_scp_MIN_TEXT_SIZE 0
+
+#define _hrt_isp_css_text_to_ddr(to, from, size, cell) \
+ do { \
+ unsigned int min_size = HRTCAT(cell, _MIN_TEXT_SIZE); \
+ target_addr = hrt_isp_css_mm_alloc(HRTMAX(size, min_size)); \
+ assert(!min_size || size < min_size); \
+ hrt_isp_css_mm_store(target_addr, blob + from, size); \
+ } while (0)
+#elif defined(HRT_CSIM)
+#define _hrt_isp_css_text_to_ddr(to, from, size, cell) \
+ do { \
+ unsigned int word_bytes = HIVE_ISP_DDR_WORD_BITS/8, \
+ padded_size = _hrt_ceil_div(size, word_bytes) * \
+ word_bytes, \
+ pad_bytes = padded_size - size, \
+ i; \
+ target_addr = hrt_isp_css_mm_alloc(size); \
+ hrt_isp_css_mm_store(target_addr, blob + from, size); \
+ for (i = 0; i < pad_bytes; i++) { \
+ hrt_isp_css_mm_store_char(target_addr + size + i, 0); \
+ } \
+ } while (0)
+#else
+#define _hrt_isp_css_text_to_ddr(to, from, size, cell) \
+ do { \
+ target_addr = hrt_isp_css_mm_alloc(size); \
+ hrt_isp_css_mm_store(target_addr, blob + from, size); \
+ } while (0)
+#endif
+
+#if defined(C_RUN) || defined(HRT_UNSCHED)
+#define hrt_isp_css_load_sp_program(prog) \
+({ \
+ void *dummy_addr = hrt_isp_css_mm_alloc(1); \
+ hrt_cell_load_program_id(SP, prog); \
+ dummy_addr; \
+})
+/* In crun, we let the SP do the entire download, the host
+ does nothing: */
+#define hrt_isp_css_load_isp_program_for_dma(prog) \
+ hrt_isp_css_mm_alloc(1)
+#else
+#if defined(HRT_CSIM)
+/* For csim, we use the blob transfer function to only initialize
+ * the DDR with data to avoid getting warnings on uninitialized reads
+ * originating from the icache. We also padd to the nearest DDR word boundary.
+ */
+#define hrt_isp_css_load_sp_program(prog) \
+({ \
+ void *target_addr; \
+ const char *blob = _hrt_program_blob(prog); \
+ _hrt_program_transfer_func(prog)(_hrt_isp_css_text_to_ddr, \
+ _hrt_cell_store_data_empty, \
+ _hrt_cell_zero_data_empty, \
+ _hrt_cell_write_view_table_empty, \
+ SP); \
+ hrt_cell_load_program_id(SP, prog); \
+ hrt_cell_set_icache_base_address(SP, target_addr); \
+ hrt_cell_invalidate_icache(SP); \
+ target_addr; \
+})
+#define hrt_isp_css_load_isp_program_for_dma(prog) \
+({ \
+ unsigned int padded_size, pad_bytes, i, size, \
+ ddr_word_bytes = HIVE_ISP_DDR_WORD_BITS/8; \
+ void *target_addr; \
+ const char *blob; \
+ hrt_cell_load_program_id(ISP, prog); \
+ size = hrt_embedded_program_size(prog); \
+ padded_size = _hrt_ceil_div(size, ddr_word_bytes) * ddr_word_bytes; \
+ pad_bytes = padded_size - size; \
+ target_addr = hrt_isp_css_mm_alloc(size); \
+ blob = _hrt_program_blob(prog); \
+ hrt_isp_css_mm_store(target_addr, blob, size); \
+ for (i = 0; i < pad_bytes; i++) { \
+ hrt_isp_css_mm_store_char(target_addr + size + i, 0); \
+ } \
+ target_addr; \
+})
+#else
+#define hrt_isp_css_load_sp_program(prog) \
+({ \
+ void *target_addr; \
+ const char *blob; \
+ blob = _hrt_program_blob(prog); \
+ _hrt_program_transfer_func(prog)(_hrt_isp_css_text_to_ddr, \
+ _hrt_cell_store_data, \
+ _hrt_cell_zero_data, \
+ _hrt_cell_write_view_table, \
+ SP); \
+ hrt_cell_set_icache_base_address(SP, target_addr); \
+ hrt_cell_invalidate_icache(SP); \
+ target_addr; \
+})
+#define hrt_isp_css_load_isp_program_for_dma(prog) \
+ _hrt_isp_css_load_isp_program_for_dma(_hrt_program_blob(prog), \
+ hrt_embedded_program_size(prog))
+static inline void *
+_hrt_isp_css_load_isp_program_for_dma(const char *blob, unsigned int size)
+{
+ void *target_addr;
+ target_addr = hrt_isp_css_mm_alloc(size);
+ hrt_isp_css_mm_store(target_addr, blob, size);
+ return target_addr;
+}
+#endif /* HRT_CSIM */
+#endif /* C_RUN || HRT_UNSCHED */
+
+#endif /* _HIVE_ISP_CSS_PROGRAM_LOAD_HRT_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_monitors_types_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_monitors_types_hrt.h
new file mode 100644
index 0000000..cdd17cf
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_monitors_types_hrt.h
@@ -0,0 +1,71 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_streaming_monitors_types_hrt_h
+#define _hive_isp_css_streaming_monitors_types_hrt_h
+
+#define _hive_str_mon_valid_offset 0
+#define _hive_str_mon_accept_offset 1
+
+#define SP_STR_MON_PORT_SND_PIF_A 0
+#define SP_STR_MON_PORT_RCV_PIF_A 1
+#define SP_STR_MON_PORT_SND_SIF 2
+#define SP_STR_MON_PORT_RCV_SIF 3
+#define SP_STR_MON_PORT_SND_MC 4
+#define SP_STR_MON_PORT_RCV_MC 5
+#define SP_STR_MON_PORT_SND_DMA 6
+#define SP_STR_MON_PORT_RCV_DMA 7
+#define SP_STR_MON_PORT_SND_GDC 8
+#define SP_STR_MON_PORT_RCV_GDC 9
+#define SP_STR_MON_PORT_SND_ISP 10
+#define SP_STR_MON_PORT_RCV_ISP 11
+#define SP_STR_MON_PORT_SND_GPD 12
+#define SP_STR_MON_PORT_RCV_GPD 13
+#define SP_STR_MON_PORT_SND_PIF_B 14
+#define SP_STR_MON_PORT_RCV_PIF_B 15
+
+#define MOD_STR_MON_PORT_SND_PIF_A 0
+#define MOD_STR_MON_PORT_RCV_PIF_A 1
+#define MOD_STR_MON_PORT_SND_SIF 2
+#define MOD_STR_MON_PORT_RCV_SIF 3
+#define MOD_STR_MON_PORT_SND_MC 4
+#define MOD_STR_MON_PORT_RCV_MC 5
+#define MOD_STR_MON_PORT_SND_DMA 6
+#define MOD_STR_MON_PORT_RCV_DMA 7
+#define MOD_STR_MON_PORT_SND_GDC 8
+#define MOD_STR_MON_PORT_RCV_GDC 9
+#define MOD_STR_MON_PORT_SND_CSS_REC 10
+
+#define ISP_STR_MON_PORT_SND_PIF_A 0
+#define ISP_STR_MON_PORT_RCV_PIF_A 1
+#define ISP_STR_MON_PORT_SND_PIF_B 2
+#define ISP_STR_MON_PORT_RCV_PIF_B 3
+#define ISP_STR_MON_PORT_SND_DMA 4
+#define ISP_STR_MON_PORT_RCV_DMA 5
+#define ISP_STR_MON_PORT_SND_GDC 6
+#define ISP_STR_MON_PORT_RCV_GDC 7
+#define ISP_STR_MON_PORT_SND_GPD 8
+#define ISP_STR_MON_PORT_RCV_GPD 9
+#define ISP_STR_MON_PORT_SND_SP 10
+#define ISP_STR_MON_PORT_RCV_SP 11
+
+#endif /* _hive_isp_css_streaming_monitors_types_hrt_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_to_mipi_types_hrt.h b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_to_mipi_types_hrt.h
new file mode 100644
index 0000000..3d07f2c
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/hive_isp_css_streaming_to_mipi_types_hrt.h
@@ -0,0 +1,36 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
+#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
+
+#include <streaming_to_mipi_defs.h>
+
+#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
+#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
+
+#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB \
+ (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
+#define _HIVE_STR_TO_MIPI_DATA_B_LSB \
+ (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
+
+#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/if_defs.h b/drivers/media/video/atomisp/include/css_hrt/if_defs.h
new file mode 100644
index 0000000..7d625da
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/if_defs.h
@@ -0,0 +1,72 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _IF_DEFS_H
+#define _IF_DEFS_H
+
+/* Hardware registers */
+#define HIVE_IF_RESET_ADDRESS 0x000
+#define HIVE_IF_START_LINE_ADDRESS 0x004
+#define HIVE_IF_START_COLUMN_ADDRESS 0x008
+#define HIVE_IF_CROPPED_HEIGHT_ADDRESS 0x00C
+#define HIVE_IF_CROPPED_WIDTH_ADDRESS 0x010
+#define HIVE_IF_VERTICAL_DECIMATION_ADDRESS 0x014
+#define HIVE_IF_HORIZONTAL_DECIMATION_ADDRESS 0x018
+#define HIVE_IF_H_DEINTERLEAVING_ADDRESS 0x01C
+#define HIVE_IF_LEFTPADDING_WIDTH_ADDRESS 0x020
+#define HIVE_IF_END_OF_LINE_OFFSET_ADDRESS 0x024
+#define HIVE_IF_VMEM_START_ADDRESS_ADDRESS 0x028
+#define HIVE_IF_VMEM_END_ADDRESS_ADDRESS 0x02C
+#define HIVE_IF_VMEM_INCREMENT_ADDRESS 0x030
+#define HIVE_IF_YUV_420_FORMAT_ADDRESS 0x034
+#define HIVE_IF_VSYNCK_ACTIVE_LOW_ADDRESS 0x038
+#define HIVE_IF_HSYNCK_ACTIVE_LOW_ADDRESS 0x03C
+#define HIVE_IF_ALLOW_FIFO_OVERFLOW_ADDRESS 0x040
+#define HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS 0x044
+#define HIVE_IF_V_DEINTERLEAVING_ADDRESS 0x048
+#define HIVE_IF_FSM_SYNC_STATUS 0x100
+#define HIVE_IF_FSM_SYNC_COUNTER 0x104
+#define HIVE_IF_FSM_CROP_STATUS 0x108
+#define HIVE_IF_FSM_CROP_LINE_COUNTER 0x10C
+#define HIVE_IF_FSM_CROP_PIXEL_COUNTER 0x110
+#define HIVE_IF_FSM_DEINTERLEAVING_IDX 0x114
+#define HIVE_IF_FSM_DECIMATION_H_COUNTER 0x118
+#define HIVE_IF_FSM_DECIMATION_V_COUNTER 0x11C
+#define HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER 0x120
+#define HIVE_IF_FSM_PADDING_STATUS 0x124
+#define HIVE_IF_FSM_PADDING_ELEMENT_COUNTER 0x128
+#define HIVE_IF_FSM_VECTOR_SUPPORT_ERROR 0x12C
+#define HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL 0x130
+#define HIVE_IF_FSM_VECTOR_SUPPORT 0x134
+#define HIVE_IF_FIFO_SENSOR_DATA_LOST 0x138
+
+/* Registers only for simulation */
+#define HIVE_IF_CRUN_MODE_ADDRESS 0x04C
+#define HIVE_IF_DUMP_OUTPUT_ADDRESS 0x050
+
+#define HIVE_IF_FRAME_REQUEST 0xA000
+#define HIVE_IF_LINES_REQUEST 0xB000
+#define HIVE_IF_VECTORS_REQUEST 0xC000
+
+#define _HRT_IF_VEC_ALIGN(if_id) HRTCAT(if_id, _vector_alignment)
+
+#endif /* _IF_DEFS_H */
diff --git a/drivers/media/video/atomisp/include/css_hrt/irq_controller_defs.h b/drivers/media/video/atomisp/include/css_hrt/irq_controller_defs.h
new file mode 100644
index 0000000..9c05a50
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/irq_controller_defs.h
@@ -0,0 +1,35 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _irq_controller_defs_h
+#define _irq_controller_defs_h
+
+#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0
+#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1
+#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2
+#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3
+#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4
+#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5
+
+#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
+
+#endif /* _irq_controller_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/isp2300_medfield_params.h b/drivers/media/video/atomisp/include/css_hrt/isp2300_medfield_params.h
new file mode 100644
index 0000000..7130e80
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/isp2300_medfield_params.h
@@ -0,0 +1,177 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+/* Version */
+#define ISP_VERSION RTL_VERSION
+
+/* Cell name */
+
+#define ISP_CELL_TYPE isp2300_medfield
+#define ISP_VMEM simd_vmem
+#define _HRT_ISP_VMEM isp2300_medfield_simd_vmem
+
+/* instruction pipeline depth */
+#define ISP_BRANCHDELAY 3
+
+/* bus */
+#define ISP_BUS_PROT CIO
+#define ISP_BUS_WIDTH 32
+#define ISP_BUS_ADDR_WIDTH 32
+#define ISP_BUS_BURST_SIZE 1
+
+/* data-path */
+#define ISP_SCALAR_WIDTH 32
+#define ISP_SLICE_NELEMS 4
+#define ISP_VEC_NELEMS 64
+#define ISP_VEC_ELEMBITS 14
+#define ISP_VEC_ELEM8BITS 16
+#define ISP_ALPHA_BLEND_SHIFT 13
+
+/* memories */
+#define ISP_DMEM_DEPTH 4096
+#define ISP_VMEM_DEPTH 2048
+#define ISP_VMEM_ELEMBITS 14
+#define ISP_VMEM_ELEM_PRECISION 14
+#define ISP_PMEM_DEPTH 2048
+#define ISP_PMEM_WIDTH 448
+#define ISP_VAMEM_ADDRESS_BITS 13
+#define ISP_VAMEM_ELEMBITS 12
+#define ISP_VAMEM_DEPTH 4096
+#define ISP_VAMEM_ALIGNMENT 2
+#define ISP_VA_ADDRESS_WIDTH 896
+#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS
+
+/* program counter */
+#define ISP_PC_WIDTH 12
+
+/* RSN pipelining */
+#define ISP_RSN_PIPE 0
+
+/* shrink instruction set */
+#define ISP_SHRINK_IS 0
+
+/* Template experiments */
+#define ISP_HAS_VARU_SIMD_IS1 0
+#define ISP_HAS_SIMD_IS5 1
+#define ISP_HAS_SIMD6_FLGU 0
+#define ISP_HAS_VALSU 1
+#define ISP_SRU_GUARDING 1
+#define ISP_VRF_RAM 1
+#define ISP_SRF_RAM 1
+#define ISP_REDUCE_VARUS 0
+#define ISP_COMBINE_MAC_SHIFT 0
+#define ISP_COMBINE_MAC_VARU 1
+#define ISP_COMBINE_SHIFT_VARU 0
+#define ISP_SLICE_LATENCY 1
+#define ISP_RFSPLIT_EXP 0
+#define ISP_SPILL_MEM_EXP 0
+#define ISP_VHSU_NO_WIDE 0
+#define ISP_NO_SLICE 0
+#define ISP_BLOCK_SLICE 0
+#define ISP_IF 1
+#define ISP_IF_B 1
+#define ISP_DMA 0
+#define ISP_OF 0
+#define ISP_SYS_OF 1
+#define ISP_GDC 1
+#define ISP_GPIO 1
+#define ISP_SP 1
+#define ISP_HAS_IRQ 1
+
+/* derived values */
+#define ISP_VEC_WIDTH 896
+#define ISP_SLICE_WIDTH 56
+#define ISP_VMEM_WIDTH 896
+#define ISP_SIMDLSU 1
+#define ISP_LSU_IMM_BITS 12
+
+/* convenient shortcuts for software*/
+#define ISP_NWAY ISP_VEC_NELEMS
+#define NBITS ISP_VEC_ELEMBITS
+
+#define _isp_ceil_div(a, b) (((a)+(b)-1)/(b))
+
+#ifdef C_RUN
+#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8)
+#define ISP_VMEM_ALIGN (_isp_ceil_div(ISP_VMEM_WIDTH, 64)*8)
+#else
+#define ISP_VEC_ALIGN 128
+#define ISP_VMEM_ALIGN ISP_VEC_ALIGN
+#endif
+
+/* HRT specific vector support */
+#define isp2300_medfield_vector_alignment ISP_VEC_ALIGN
+#define isp2300_medfield_vector_elem_bits ISP_VMEM_ELEMBITS
+#define isp2300_medfield_vector_elem_precision ISP_VMEM_ELEM_PRECISION
+#define isp2300_medfield_vector_num_elems ISP_VEC_NELEMS
+
+/* register file sizes */
+#define ISP_RF0_SIZE 64
+#define ISP_RF1_SIZE 8
+#define ISP_RF2_SIZE 64
+#define ISP_RF3_SIZE 32
+#define ISP_RF4_SIZE 32
+#define ISP_RF5_SIZE 32
+#define ISP_RF6_SIZE 16
+#define ISP_VRF0_SIZE 16
+#define ISP_VRF1_SIZE 16
+#define ISP_VRF2_SIZE 16
+#define ISP_VRF3_SIZE 16
+#define ISP_VRF4_SIZE 16
+#define ISP_VRF5_SIZE 16
+#define ISP_VRF6_SIZE 16
+#define ISP_VRF7_SIZE 16
+#define ISP_VRF8_SIZE 16
+#define ISP_SRF0_SIZE 64
+#define ISP_SRF1_SIZE 64
+#define ISP_FRF0_SIZE 16
+#define ISP_FRF1_SIZE 16
+/* register file read latency */
+#define ISP_VRF0_READ_LAT 0
+#define ISP_VRF1_READ_LAT 0
+#define ISP_VRF2_READ_LAT 0
+#define ISP_VRF3_READ_LAT 0
+#define ISP_VRF4_READ_LAT 0
+#define ISP_VRF5_READ_LAT 0
+#define ISP_VRF6_READ_LAT 0
+#define ISP_VRF7_READ_LAT 0
+#define ISP_VRF8_READ_LAT 0
+#define ISP_SRF0_READ_LAT 0
+#define ISP_SRF1_READ_LAT 0
+/* immediate sizes */
+#define ISP_IS1_IMM_BITS 13
+#define ISP_IS2_IMM_BITS 10
+#define ISP_IS3_IMM_BITS 7
+#define ISP_IS4_IMM_BITS 7
+#define ISP_IS5_IMM_BITS 13
+#define ISP_IS6_IMM_BITS 7
+#define ISP_IS7_IMM_BITS 7
+#define ISP_IS8_IMM_BITS 7
+#define ISP_IS9_IMM_BITS 7
+/* fifo depths */
+#define ISP_IF_FIFO_DEPTH 0
+#define ISP_IF_B_FIFO_DEPTH 0
+#define ISP_DMA_FIFO_DEPTH 0
+#define ISP_OF_FIFO_DEPTH 0
+#define ISP_GDC_FIFO_DEPTH 0
+#define ISP_GPIO_FIFO_DEPTH 0
+#define ISP_SP_FIFO_DEPTH 0
diff --git a/drivers/media/video/atomisp/include/css_hrt/master_port.h b/drivers/media/video/atomisp/include/css_hrt/master_port.h
new file mode 100644
index 0000000..706228a
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/master_port.h
@@ -0,0 +1,148 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HRT_MASTER_PORT_H_
+#define _HRT_MASTER_PORT_H_
+
+/* This file contains the end of the HRT.
+ * Here we split between the hardware implementation (memcpy / assignments)
+ * and the software backends (_hrt_master_port_load / _hrt_master_port_store)
+ */
+
+/* If HRT_USE_VIR_ADDRS is defined, the OS needs to implement the following
+ functions for us:
+ _hrt_master_port_store_8(addr,data)
+ _hrt_master_port_store_16(addr,data)
+ _hrt_master_port_store_32(addr,data)
+ _hrt_master_port_load_8(addr)
+ _hrt_master_port_uload_8(addr)
+ _hrt_master_port_load_16(addr)
+ _hrt_master_port_uload_16(addr)
+ _hrt_master_port_load_32(addr)
+ _hrt_master_port_uload_32(addr)
+ _hrt_master_port_store_8_volatile(addr,data)
+ _hrt_master_port_load_8_volatile(addr)
+ _hrt_master_port_uload_8_volatile(addr)
+ _hrt_master_port_store_16_volatile(addr,data)
+ _hrt_master_port_load_16_volatile(addr)
+ _hrt_master_port_uload_16_volatile(addr)
+ _hrt_master_port_store_32_volatile(addr,data)
+ _hrt_master_port_load_32_volatile(addr)
+ _hrt_master_port_uload_32_volatile(addr)
+ _hrt_mem_store(addr,data,size)
+ _hrt_mem_load(addr,data,size)
+ _hrt_mem_set(addr,val,size)
+*/
+
+#define hrt_master_port_store_8(addr, data) \
+ _hrt_master_port_store_8(addr, data)
+#define hrt_master_port_store_16(addr, data) \
+ _hrt_master_port_store_16(addr, data)
+#define hrt_master_port_store_32(addr, data) \
+ _hrt_master_port_store_32(addr, data)
+#define hrt_master_port_load_8(addr) \
+ _hrt_master_port_load_8(addr)
+#define hrt_master_port_load_16(addr) \
+ _hrt_master_port_load_16(addr)
+#define hrt_master_port_load_32(addr) \
+ _hrt_master_port_load_32(addr)
+#define hrt_master_port_uload_8(addr) \
+ _hrt_master_port_uload_8(addr)
+#define hrt_master_port_uload_16(addr) \
+ _hrt_master_port_uload_16(addr)
+#define hrt_master_port_uload_32(addr) \
+ _hrt_master_port_uload_32(addr)
+
+#define hrt_master_port_store(addr, data, bytes) \
+ _hrt_master_port_unaligned_store((void *)(addr), \
+ (const void *)(data), bytes)
+#define hrt_master_port_load(addr, data, bytes) \
+ _hrt_master_port_unaligned_load((const void *)(addr), \
+ (void *)(data), bytes)
+#define hrt_master_port_set(addr, data, bytes) \
+ _hrt_master_port_unaligned_set((void *)(addr), \
+ (int)(data), bytes)
+
+#ifdef HRT_HW
+/* on real hardware, we cannot print messages, so we get rid of them here. */
+#define _hrt_master_port_unaligned_store_msg(a, d, s, m) \
+ _hrt_master_port_unaligned_store(a, d, s)
+#define _hrt_master_port_unaligned_load_msg(a, d, s, m) \
+ _hrt_master_port_unaligned_load(a, d, s)
+#define _hrt_master_port_unaligned_set_msg(a, d, s, m) \
+ _hrt_master_port_unaligned_set(a, d, s)
+#define _hrt_master_port_store_8_msg(a, d, m) \
+ _hrt_master_port_store_8(a, d)
+#define _hrt_master_port_store_16_msg(a, d, m) \
+ _hrt_master_port_store_16(a, d)
+#define _hrt_master_port_store_32_msg(a, d, m) \
+ _hrt_master_port_store_32(a, d)
+#define _hrt_master_port_load_8_msg(a, m) \
+ _hrt_master_port_load_8(a)
+#define _hrt_master_port_load_16_msg(a, m) \
+ _hrt_master_port_load_16(a)
+#define _hrt_master_port_load_32_msg(a, m) \
+ _hrt_master_port_load_32(a)
+#define _hrt_master_port_uload_8_msg(a, m) \
+ _hrt_master_port_uload_8(a)
+#define _hrt_master_port_uload_16_msg(a, m) \
+ _hrt_master_port_uload_16(a)
+#define _hrt_master_port_uload_32_msg(a, m) \
+ _hrt_master_port_uload_32(a)
+#define _hrt_master_port_store_8_volatile_msg(a, d, m) \
+ _hrt_master_port_store_8_volatile(a, d)
+#define _hrt_master_port_load_8_volatile_msg(a, m) \
+ _hrt_master_port_load_8_volatile(a)
+#define _hrt_master_port_uload_8_volatile_msg(a, m) \
+ _hrt_master_port_uload_8_volatile(a)
+#define _hrt_master_port_store_16_volatile_msg(a, d, m) \
+ _hrt_master_port_store_16_volatile(a, d)
+#define _hrt_master_port_load_16_volatile_msg(a, m) \
+ _hrt_master_port_load_16_volatile(a)
+#define _hrt_master_port_uload_16_volatile_msg(a, m) \
+ _hrt_master_port_uload_16_volatile(a)
+#define _hrt_master_port_store_32_volatile_msg(a, d, m) \
+ _hrt_master_port_store_32_volatile(a, d)
+#define _hrt_master_port_load_32_volatile_msg(a, m) \
+ _hrt_master_port_load_32_volatile(a)
+#define _hrt_master_port_uload_32_volatile_msg(a, m) \
+ _hrt_master_port_uload_32_volatile(a)
+/* reduce number of functions */
+#define _hrt_master_port_unaligned_store(address, data, size) \
+ hrt_mem_store(address, data, size)
+#define _hrt_master_port_unaligned_load(address, data, size) \
+ hrt_mem_load(address, data, size)
+#define _hrt_master_port_unaligned_set(address, data, size) \
+ hrt_mem_set(address, data, size)
+#endif /* HRT_HW */
+
+#if defined(__HIVECC)
+#include "master_port_hivecc.h"
+#elif defined(HRT_USE_VIR_ADDRS)
+/* do nothing, hrt backend is already included */
+#elif defined(HRT_HW)
+#include "master_port_hw.h"
+#else
+#include "master_port_sim.h"
+#endif
+
+#endif /* _HRT_MASTER_PORT_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/mmu_defs.h b/drivers/media/video/atomisp/include/css_hrt/mmu_defs.h
new file mode 100644
index 0000000..200541a
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/mmu_defs.h
@@ -0,0 +1,31 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _mmu_defs_h
+#define _mmu_defs_h
+
+#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0
+#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1
+
+#define _HRT_MMU_REG_ALIGN 4
+
+#endif /* _mmu_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/sp.map.h b/drivers/media/video/atomisp/include/css_hrt/sp.map.h
new file mode 100644
index 0000000..eddc18b
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/sp.map.h
@@ -0,0 +1,2349 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+/*
+ * Scaler processor variable defines
+ */
+#ifndef _SP_MAP_H_
+#define _SP_MAP_H_
+
+#ifndef USE_DYNAMIC_BIN
+#include "./sp.blob.h"
+#endif
+
+#ifndef _hrt_dummy_use_blob_sp
+#define _hrt_dummy_use_blob_sp()
+#endif
+
+#define _hrt_cell_load_program_sp(proc) \
+ _hrt_cell_load_program_embedded(proc, sp)
+
+#if defined(HIVE_MEM_sp_uds_obuf_offset_u) && \
+ (HIVE_ADDR_sp_uds_obuf_offset_u != 0x357C || \
+ HIVE_SIZE_sp_uds_obuf_offset_u != 44)
+#error Symbol sp_uds_obuf_offset_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_obuf_offset_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_obuf_offset_u 0x357C
+#define HIVE_SIZE_sp_uds_obuf_offset_u 44
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_u) && \
+ (HIVE_ADDR_sp_si_bg_u != 0x35A8 || \
+ HIVE_SIZE_sp_si_bg_u != 4)
+#error Symbol sp_si_bg_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_u 0x35A8
+#define HIVE_SIZE_sp_si_bg_u 4
+#endif
+
+/* function sp_dma_proxy_read: D0B */
+#if defined(HIVE_MEM_sp_vf_crop_pos_x) && \
+ (HIVE_ADDR_sp_vf_crop_pos_x != 0x3178 || \
+ HIVE_SIZE_sp_vf_crop_pos_x != 4)
+#error Symbol sp_vf_crop_pos_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vf_crop_pos_x scalar_processor_dmem
+#define HIVE_ADDR_sp_vf_crop_pos_x 0x3178
+#define HIVE_SIZE_sp_vf_crop_pos_x 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_v_addr) && \
+ (HIVE_ADDR_sp_input_v_addr != 0x317C || \
+ HIVE_SIZE_sp_input_v_addr != 4)
+#error Symbol sp_input_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_v_addr 0x317C
+#define HIVE_SIZE_sp_input_v_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_icx_left_rounded_y) && \
+ (HIVE_ADDR_sp_uds_icx_left_rounded_y != 0x35AC || \
+ HIVE_SIZE_sp_uds_icx_left_rounded_y != 4)
+#error Symbol sp_uds_icx_left_rounded_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_icx_left_rounded_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_icx_left_rounded_y 0x35AC
+#define HIVE_SIZE_sp_uds_icx_left_rounded_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_horiproj_num) && \
+ (HIVE_ADDR_sp_sdis_horiproj_num != 0x3180 || \
+ HIVE_SIZE_sp_sdis_horiproj_num != 4)
+#error Symbol sp_sdis_horiproj_num occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_horiproj_num scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_horiproj_num 0x3180
+#define HIVE_SIZE_sp_sdis_horiproj_num 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_batr) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_batr != 0x35B0 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_batr != 4)
+#error Symbol sp_frame_ptr_qplane_batr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_batr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_batr 0x35B0
+#define HIVE_SIZE_sp_frame_ptr_qplane_batr 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_u) && \
+ (HIVE_ADDR_sp_si_blend_overlay_u != 0x35B4 || \
+ HIVE_SIZE_sp_si_blend_overlay_u != 4)
+#error Symbol sp_si_blend_overlay_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_u 0x35B4
+#define HIVE_SIZE_sp_si_blend_overlay_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_yuv420) && \
+ (HIVE_ADDR_sp_if_b_yuv420 != 0x35B8 || \
+ HIVE_SIZE_sp_if_b_yuv420 != 4)
+#error Symbol sp_if_b_yuv420 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_yuv420 scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_yuv420 0x35B8
+#define HIVE_SIZE_sp_if_b_yuv420 4
+#endif
+
+#if defined(HIVE_MEM_dma_proxy_status) && \
+ (HIVE_ADDR_dma_proxy_status != 0x4C || \
+ HIVE_SIZE_dma_proxy_status != 4)
+#error Symbol dma_proxy_status occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_dma_proxy_status scalar_processor_dmem
+#define HIVE_ADDR_dma_proxy_status 0x4C
+#define HIVE_SIZE_dma_proxy_status 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_gr) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_gr != 0x35BC || \
+ HIVE_SIZE_sp_frame_ptr_plane_gr != 4)
+#error Symbol sp_frame_ptr_plane_gr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_gr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_gr 0x35BC
+#define HIVE_SIZE_sp_frame_ptr_plane_gr 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_bytes_available) && \
+ (HIVE_ADDR_sp_bin_copy_bytes_available != 0x3184 || \
+ HIVE_SIZE_sp_bin_copy_bytes_available != 4)
+#error Symbol sp_bin_copy_bytes_available occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_bytes_available scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_bytes_available 0x3184
+#define HIVE_SIZE_sp_bin_copy_bytes_available 4
+#endif
+
+/* function sp_start_isp: 5 */
+#if defined(HIVE_MEM_sp_error) && \
+ (HIVE_ADDR_sp_error != 0x3534 || \
+ HIVE_SIZE_sp_error != 4)
+#error Symbol sp_error occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_error scalar_processor_dmem
+#define HIVE_ADDR_sp_error 0x3534
+#define HIVE_SIZE_sp_error 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_v) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_v != 0x35C0 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_v != 4)
+#error Symbol sp_frame_ptr_vfout_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_v 0x35C0
+#define HIVE_SIZE_sp_frame_ptr_vfout_v 4
+#endif
+
+/* function _initialize_sdis_coefficients: F1D */
+/* function _clear_vectors: EA8 */
+#if defined(HIVE_MEM_sp_frame_ptr_uv_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_prev != 0x35C4 || \
+ HIVE_SIZE_sp_frame_ptr_uv_prev != 4)
+#error Symbol sp_frame_ptr_uv_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_prev 0x35C4
+#define HIVE_SIZE_sp_frame_ptr_uv_prev 4
+#endif
+
+#if defined(HIVE_MEM_hres_in) && \
+ (HIVE_ADDR_hres_in != 0x3188 || \
+ HIVE_SIZE_hres_in != 4)
+#error Symbol hres_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_hres_in scalar_processor_dmem
+#define HIVE_ADDR_hres_in 0x3188
+#define HIVE_SIZE_hres_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_comp) && \
+ (HIVE_ADDR_sp_mipi_comp != 0x318C || \
+ HIVE_SIZE_sp_mipi_comp != 4)
+#error Symbol sp_mipi_comp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_comp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_comp 0x318C
+#define HIVE_SIZE_sp_mipi_comp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_v) && \
+ (HIVE_ADDR_sp_frame_ptr_v != 0x35C8 || \
+ HIVE_SIZE_sp_frame_ptr_v != 4)
+#error Symbol sp_frame_ptr_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v 0x35C8
+#define HIVE_SIZE_sp_frame_ptr_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_cropped_height) && \
+ (HIVE_ADDR_sp_if_a_cropped_height != 0x35CC || \
+ HIVE_SIZE_sp_if_a_cropped_height != 4)
+#error Symbol sp_if_a_cropped_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_cropped_height scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_cropped_height 0x35CC
+#define HIVE_SIZE_sp_if_a_cropped_height 4
+#endif
+
+/* function isp_pregdc_var_sp_main: 3373 */
+/* function hrt_isp_css_sp_store_isp_code: 3C65 */
+/* function sp_dma_proxy_init_entry: C42 */
+#ifdef HIVE_ADDR_sp_dma_proxy_init_entry
+#error Symbol sp_dma_proxy_init_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_dma_proxy_init_entry 0xC42
+#endif
+
+#if defined(HIVE_MEM_vf_log_scale) && \
+ (HIVE_ADDR_vf_log_scale != 0x3190 || \
+ HIVE_SIZE_vf_log_scale != 4)
+#error Symbol vf_log_scale occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vf_log_scale scalar_processor_dmem
+#define HIVE_ADDR_vf_log_scale 0x3190
+#define HIVE_SIZE_vf_log_scale 4
+#endif
+
+#if defined(HIVE_MEM_sp_enable_xnr) && \
+ (HIVE_ADDR_sp_enable_xnr != 0x35D0 || \
+ HIVE_SIZE_sp_enable_xnr != 4)
+#error Symbol sp_enable_xnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_enable_xnr scalar_processor_dmem
+#define HIVE_ADDR_sp_enable_xnr 0x35D0
+#define HIVE_SIZE_sp_enable_xnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_bayer1) && \
+ (HIVE_ADDR_sp_frame_ptr_bayer1 != 0x35D4 || \
+ HIVE_SIZE_sp_frame_ptr_bayer1 != 4)
+#error Symbol sp_frame_ptr_bayer1 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_bayer1 scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_bayer1 0x35D4
+#define HIVE_SIZE_sp_frame_ptr_bayer1 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_obuf_offset_y) && \
+ (HIVE_ADDR_sp_uds_obuf_offset_y != 0x35D8 || \
+ HIVE_SIZE_sp_uds_obuf_offset_y != 44)
+#error Symbol sp_uds_obuf_offset_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_obuf_offset_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_obuf_offset_y 0x35D8
+#define HIVE_SIZE_sp_uds_obuf_offset_y 44
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_u) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_u != 0x3604 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_u != 4)
+#error Symbol sp_frame_ptr_overlay_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_u 0x3604
+#define HIVE_SIZE_sp_frame_ptr_overlay_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_num_lanes) && \
+ (HIVE_ADDR_sp_mipi_num_lanes != 0x3194 || \
+ HIVE_SIZE_sp_mipi_num_lanes != 4)
+#error Symbol sp_mipi_num_lanes occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_num_lanes scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_num_lanes 0x3194
+#define HIVE_SIZE_sp_mipi_num_lanes 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_iy_topleft_u) && \
+ (HIVE_ADDR_sp_uds_iy_topleft_u != 0x3608 || \
+ HIVE_SIZE_sp_uds_iy_topleft_u != 4)
+#error Symbol sp_uds_iy_topleft_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_iy_topleft_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_iy_topleft_u 0x3608
+#define HIVE_SIZE_sp_uds_iy_topleft_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_ch_id) && \
+ (HIVE_ADDR_sp_ch_id != 0x3198 || \
+ HIVE_SIZE_sp_ch_id != 4)
+#error Symbol sp_ch_id occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_ch_id scalar_processor_dmem
+#define HIVE_ADDR_sp_ch_id 0x3198
+#define HIVE_SIZE_sp_ch_id 4
+#endif
+
+#if defined(HIVE_MEM_num_handled_dma_acks) && \
+ (HIVE_ADDR_num_handled_dma_acks != 0x3070 || \
+ HIVE_SIZE_num_handled_dma_acks != 4)
+#error Symbol num_handled_dma_acks occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_num_handled_dma_acks scalar_processor_dmem
+#define HIVE_ADDR_num_handled_dma_acks 0x3070
+#define HIVE_SIZE_num_handled_dma_acks 4
+#endif
+
+#if defined(HIVE_MEM__hrt_isp_css_curr_fmt_type_sp) && \
+ (HIVE_ADDR__hrt_isp_css_curr_fmt_type_sp != 0x319C || \
+ HIVE_SIZE__hrt_isp_css_curr_fmt_type_sp != 4)
+#error Symbol _hrt_isp_css_curr_fmt_type_sp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM__hrt_isp_css_curr_fmt_type_sp scalar_processor_dmem
+#define HIVE_ADDR__hrt_isp_css_curr_fmt_type_sp 0x319C
+#define HIVE_SIZE__hrt_isp_css_curr_fmt_type_sp 4
+#endif
+
+/* function isp_video_online_sp_main: 299F */
+/* function isp_copy_var_sp_main: 18B2 */
+/* function isp_xnr_var_sp_main: 3891 */
+#if defined(HIVE_MEM_sp_uds_woix) && \
+ (HIVE_ADDR_sp_uds_woix != 0x360C || \
+ HIVE_SIZE_sp_uds_woix != 4)
+#error Symbol sp_uds_woix occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix 0x360C
+#define HIVE_SIZE_sp_uds_woix 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_vblank_cycles) && \
+ (HIVE_ADDR_sp_sync_gen_vblank_cycles != 0x31A0 || \
+ HIVE_SIZE_sp_sync_gen_vblank_cycles != 4)
+#error Symbol sp_sync_gen_vblank_cycles occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_vblank_cycles scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_vblank_cycles 0x31A0
+#define HIVE_SIZE_sp_sync_gen_vblank_cycles 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_gb) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_gb != 0x3610 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_gb != 4)
+#error Symbol sp_frame_ptr_qplane_gb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_gb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_gb 0x3610
+#define HIVE_SIZE_sp_frame_ptr_qplane_gb 4
+#endif
+
+#if defined(HIVE_MEM_sp_prbs_seed) && \
+ (HIVE_ADDR_sp_prbs_seed != 0x31A4 || \
+ HIVE_SIZE_sp_prbs_seed != 4)
+#error Symbol sp_prbs_seed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_prbs_seed scalar_processor_dmem
+#define HIVE_ADDR_sp_prbs_seed 0x31A4
+#define HIVE_SIZE_sp_prbs_seed 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_x_mask) && \
+ (HIVE_ADDR_sp_tpg_x_mask != 0x31A8 || \
+ HIVE_SIZE_sp_tpg_x_mask != 4)
+#error Symbol sp_tpg_x_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_x_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_x_mask 0x31A8
+#define HIVE_SIZE_sp_tpg_x_mask 4
+#endif
+
+#if defined(HIVE_MEM_xmem_bin_addr) && \
+ (HIVE_ADDR_xmem_bin_addr != 0x31AC || \
+ HIVE_SIZE_xmem_bin_addr != 4)
+#error Symbol xmem_bin_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_xmem_bin_addr scalar_processor_dmem
+#define HIVE_ADDR_xmem_bin_addr 0x31AC
+#define HIVE_SIZE_xmem_bin_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woiy) && \
+ (HIVE_ADDR_sp_uds_woiy != 0x3614 || \
+ HIVE_SIZE_sp_uds_woiy != 4)
+#error Symbol sp_uds_woiy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woiy scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woiy 0x3614
+#define HIVE_SIZE_sp_uds_woiy 4
+#endif
+
+#if defined(HIVE_MEM_sp_fmt_type) && \
+ (HIVE_ADDR_sp_fmt_type != 0x31B0 || \
+ HIVE_SIZE_sp_fmt_type != 4)
+#error Symbol sp_fmt_type occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_fmt_type scalar_processor_dmem
+#define HIVE_ADDR_sp_fmt_type 0x31B0
+#define HIVE_SIZE_sp_fmt_type 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_v) && \
+ (HIVE_ADDR_sp_si_blend_overlay_v != 0x3618 || \
+ HIVE_SIZE_sp_si_blend_overlay_v != 4)
+#error Symbol sp_si_blend_overlay_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_v 0x3618
+#define HIVE_SIZE_sp_si_blend_overlay_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_vecs) && \
+ (HIVE_ADDR_sp_if_b_buf_vecs != 0x361C || \
+ HIVE_SIZE_sp_if_b_buf_vecs != 4)
+#error Symbol sp_if_b_buf_vecs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_vecs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_vecs 0x361C
+#define HIVE_SIZE_sp_if_b_buf_vecs 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_start_index) && \
+ (HIVE_ADDR_sp_if_a_buf_start_index != 0x3620 || \
+ HIVE_SIZE_sp_if_a_buf_start_index != 4)
+#error Symbol sp_if_a_buf_start_index occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_start_index scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_start_index 0x3620
+#define HIVE_SIZE_sp_if_a_buf_start_index 4
+#endif
+
+/* function isp_postgdc_var_sp_main: 3672 */
+#if defined(HIVE_MEM_sp_frame_ptr_plane_batr) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_batr != 0x3624 || \
+ HIVE_SIZE_sp_frame_ptr_plane_batr != 4)
+#error Symbol sp_frame_ptr_plane_batr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_batr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_batr 0x3624
+#define HIVE_SIZE_sp_frame_ptr_plane_batr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_num_chunks) && \
+ (HIVE_ADDR_sp_uds_num_chunks != 0x3628 || \
+ HIVE_SIZE_sp_uds_num_chunks != 4)
+#error Symbol sp_uds_num_chunks occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_num_chunks scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_num_chunks 0x3628
+#define HIVE_SIZE_sp_uds_num_chunks 4
+#endif
+
+#if defined(HIVE_MEM_sp_obarea_lengthBQ) && \
+ (HIVE_ADDR_sp_obarea_lengthBQ != 0x31B4 || \
+ HIVE_SIZE_sp_obarea_lengthBQ != 4)
+#error Symbol sp_obarea_lengthBQ occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_obarea_lengthBQ scalar_processor_dmem
+#define HIVE_ADDR_sp_obarea_lengthBQ 0x31B4
+#define HIVE_SIZE_sp_obarea_lengthBQ 4
+#endif
+
+#if defined(HIVE_MEM_vres_in) && \
+ (HIVE_ADDR_vres_in != 0x31B8 || \
+ HIVE_SIZE_vres_in != 4)
+#error Symbol vres_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vres_in scalar_processor_dmem
+#define HIVE_ADDR_vres_in 0x31B8
+#define HIVE_SIZE_vres_in 4
+#endif
+
+#if defined(HIVE_MEM_deci_log_factor) && \
+ (HIVE_ADDR_deci_log_factor != 0x31BC || \
+ HIVE_SIZE_deci_log_factor != 4)
+#error Symbol deci_log_factor occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_deci_log_factor scalar_processor_dmem
+#define HIVE_ADDR_deci_log_factor 0x31BC
+#define HIVE_SIZE_deci_log_factor 4
+#endif
+
+#if defined(HIVE_MEM_vres) && \
+ (HIVE_ADDR_vres != 0x31C0 || \
+ HIVE_SIZE_vres != 4)
+#error Symbol vres occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vres scalar_processor_dmem
+#define HIVE_ADDR_vres 0x31C0
+#define HIVE_SIZE_vres 4
+#endif
+
+/* function isp_primary_ds_sp_main: 1CF6 */
+#if defined(HIVE_MEM_sp_uds_bpp) && \
+ (HIVE_ADDR_sp_uds_bpp != 0x362C || \
+ HIVE_SIZE_sp_uds_bpp != 4)
+#error Symbol sp_uds_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_bpp 0x362C
+#define HIVE_SIZE_sp_uds_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_bytes_copied) && \
+ (HIVE_ADDR_sp_bin_copy_bytes_copied != 0x31C4 || \
+ HIVE_SIZE_sp_bin_copy_bytes_copied != 4)
+#error Symbol sp_bin_copy_bytes_copied occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_bytes_copied scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_bytes_copied 0x31C4
+#define HIVE_SIZE_sp_bin_copy_bytes_copied 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_eol_offset) && \
+ (HIVE_ADDR_sp_if_b_buf_eol_offset != 0x3630 || \
+ HIVE_SIZE_sp_if_b_buf_eol_offset != 4)
+#error Symbol sp_if_b_buf_eol_offset occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_eol_offset scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_eol_offset 0x3630
+#define HIVE_SIZE_sp_if_b_buf_eol_offset 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_y) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_y != 0x3634 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_y != 4)
+#error Symbol sp_uds_dma_pixel_block_width_b_in_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_y 0x3634
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_bci) && \
+ (HIVE_ADDR_sp_uds_bci != 0x3638 || \
+ HIVE_SIZE_sp_uds_bci != 4)
+#error Symbol sp_uds_bci occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_bci scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_bci 0x3638
+#define HIVE_SIZE_sp_uds_bci 4
+#endif
+
+#if defined(HIVE_MEM_isp_sh_dma_cmd_buffer) && \
+ (HIVE_ADDR_isp_sh_dma_cmd_buffer != 0x3538 || \
+ HIVE_SIZE_isp_sh_dma_cmd_buffer != 4)
+#error Symbol isp_sh_dma_cmd_buffer occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_isp_sh_dma_cmd_buffer scalar_processor_dmem
+#define HIVE_ADDR_isp_sh_dma_cmd_buffer 0x3538
+#define HIVE_SIZE_isp_sh_dma_cmd_buffer 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_bg_u) && \
+ (HIVE_ADDR_sp_overlay_bg_u != 0x31C8 || \
+ HIVE_SIZE_sp_overlay_bg_u != 4)
+#error Symbol sp_overlay_bg_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_u scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_u 0x31C8
+#define HIVE_SIZE_sp_overlay_bg_u 4
+#endif
+
+/* function _initialize_macc_coefficients: ED4 */
+#if defined(HIVE_MEM_sp_if_b_left_padding) && \
+ (HIVE_ADDR_sp_if_b_left_padding != 0x363C || \
+ HIVE_SIZE_sp_if_b_left_padding != 4)
+#error Symbol sp_if_b_left_padding occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_left_padding scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_left_padding 0x363C
+#define HIVE_SIZE_sp_if_b_left_padding 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_vertcoef_vectors) && \
+ (HIVE_ADDR_sp_sdis_vertcoef_vectors != 0x31CC || \
+ HIVE_SIZE_sp_sdis_vertcoef_vectors != 4)
+#error Symbol sp_sdis_vertcoef_vectors occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_vertcoef_vectors scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_vertcoef_vectors 0x31CC
+#define HIVE_SIZE_sp_sdis_vertcoef_vectors 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_width) && \
+ (HIVE_ADDR_sp_sync_gen_width != 0x31D0 || \
+ HIVE_SIZE_sp_sync_gen_width != 4)
+#error Symbol sp_sync_gen_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_width scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_width 0x31D0
+#define HIVE_SIZE_sp_sync_gen_width 4
+#endif
+
+#if defined(HIVE_MEM_hres) && \
+ (HIVE_ADDR_hres != 0x31D4 || \
+ HIVE_SIZE_hres != 4)
+#error Symbol hres occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_hres scalar_processor_dmem
+#define HIVE_ADDR_hres 0x31D4
+#define HIVE_SIZE_hres 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv) && \
+ (HIVE_ADDR_sp_frame_ptr_uv != 0x3640 || \
+ HIVE_SIZE_sp_frame_ptr_uv != 4)
+#error Symbol sp_frame_ptr_uv occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv 0x3640
+#define HIVE_SIZE_sp_frame_ptr_uv 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_ratb) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_ratb != 0x3644 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_ratb != 4)
+#error Symbol sp_frame_ptr_qplane_ratb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_ratb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_ratb 0x3644
+#define HIVE_SIZE_sp_frame_ptr_qplane_ratb 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_icx_left_rounded_u) && \
+ (HIVE_ADDR_sp_uds_icx_left_rounded_u != 0x3648 || \
+ HIVE_SIZE_sp_uds_icx_left_rounded_u != 4)
+#error Symbol sp_uds_icx_left_rounded_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_icx_left_rounded_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_icx_left_rounded_u 0x3648
+#define HIVE_SIZE_sp_uds_icx_left_rounded_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_y) && \
+ (HIVE_ADDR_sp_si_blend_input_y != 0x364C || \
+ HIVE_SIZE_sp_si_blend_input_y != 4)
+#error Symbol sp_si_blend_input_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_y 0x364C
+#define HIVE_SIZE_sp_si_blend_input_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv_in) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_in != 0x3650 || \
+ HIVE_SIZE_sp_frame_ptr_uv_in != 4)
+#error Symbol sp_frame_ptr_uv_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_in 0x3650
+#define HIVE_SIZE_sp_frame_ptr_uv_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_cropped_width) && \
+ (HIVE_ADDR_sp_if_a_cropped_width != 0x3654 || \
+ HIVE_SIZE_sp_if_a_cropped_width != 4)
+#error Symbol sp_if_a_cropped_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_cropped_width scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_cropped_width 0x3654
+#define HIVE_SIZE_sp_if_a_cropped_width 4
+#endif
+
+/* function isp_bayer_ds_var_sp_main: 3A35 */
+#if defined(HIVE_MEM_sp_tpg_x_delta) && \
+ (HIVE_ADDR_sp_tpg_x_delta != 0x31D8 || \
+ HIVE_SIZE_sp_tpg_x_delta != 4)
+#error Symbol sp_tpg_x_delta occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_x_delta scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_x_delta 0x31D8
+#define HIVE_SIZE_sp_tpg_x_delta 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_vertproj_num) && \
+ (HIVE_ADDR_sp_sdis_vertproj_num != 0x31DC || \
+ HIVE_SIZE_sp_sdis_vertproj_num != 4)
+#error Symbol sp_sdis_vertproj_num occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_vertproj_num scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_vertproj_num 0x31DC
+#define HIVE_SIZE_sp_sdis_vertproj_num 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_yuv420) && \
+ (HIVE_ADDR_sp_if_a_yuv420 != 0x3658 || \
+ HIVE_SIZE_sp_if_a_yuv420 != 4)
+#error Symbol sp_if_a_yuv420 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_yuv420 scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_yuv420 0x3658
+#define HIVE_SIZE_sp_if_a_yuv420 4
+#endif
+
+/* function sp_dma_proxy_run_entry: 767 */
+#ifdef HIVE_ADDR_sp_dma_proxy_run_entry
+#error Symbol sp_dma_proxy_run_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_dma_proxy_run_entry 0x767
+#endif
+
+/* function isp_primary_14mp_sp_main: 13C2 */
+#if defined(HIVE_MEM_sp_frame_ptr_bayer0) && \
+ (HIVE_ADDR_sp_frame_ptr_bayer0 != 0x365C || \
+ HIVE_SIZE_sp_frame_ptr_bayer0 != 4)
+#error Symbol sp_frame_ptr_bayer0 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_bayer0 scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_bayer0 0x365C
+#define HIVE_SIZE_sp_frame_ptr_bayer0 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_overlay_y) && \
+ (HIVE_ADDR_sp_si_blend_overlay_y != 0x3660 || \
+ HIVE_SIZE_sp_si_blend_overlay_y != 4)
+#error Symbol sp_si_blend_overlay_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_overlay_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_overlay_y 0x3660
+#define HIVE_SIZE_sp_si_blend_overlay_y 4
+#endif
+
+/* function isp_preview_ds_sp_main: 238F */
+#if defined(HIVE_MEM_sp_overlay_v_addr) && \
+ (HIVE_ADDR_sp_overlay_v_addr != 0x31E0 || \
+ HIVE_SIZE_sp_overlay_v_addr != 4)
+#error Symbol sp_overlay_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_v_addr 0x31E0
+#define HIVE_SIZE_sp_overlay_v_addr 4
+#endif
+
+/* function sp_dma_proxy_wait_for_ack: C72 */
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_u) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_u != 0x3664 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_u != 4)
+#error Symbol sp_uds_dma_pixel_block_width_b_in_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_b_in_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_b_in_u 0x3664
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_b_in_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_u) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_u != 0x3668 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_u != 4)
+#error Symbol sp_frame_ptr_vfout_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_u 0x3668
+#define HIVE_SIZE_sp_frame_ptr_vfout_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_gb) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_gb != 0x366C || \
+ HIVE_SIZE_sp_frame_ptr_plane_gb != 4)
+#error Symbol sp_frame_ptr_plane_gb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_gb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_gb 0x366C
+#define HIVE_SIZE_sp_frame_ptr_plane_gb 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_uv) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_uv != 0x3670 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_uv != 4)
+#error Symbol sp_frame_ptr_vfout_uv occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_uv scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_uv 0x3670
+#define HIVE_SIZE_sp_frame_ptr_vfout_uv 4
+#endif
+
+/* function initialize_lut: F56 */
+#if defined(HIVE_MEM_input_stream_format) && \
+ (HIVE_ADDR_input_stream_format != 0x31E4 || \
+ HIVE_SIZE_input_stream_format != 4)
+#error Symbol input_stream_format occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_input_stream_format scalar_processor_dmem
+#define HIVE_ADDR_input_stream_format 0x31E4
+#define HIVE_SIZE_input_stream_format 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_r) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_r != 0x3674 || \
+ HIVE_SIZE_sp_frame_ptr_plane_r != 4)
+#error Symbol sp_frame_ptr_plane_r occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_r scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_r 0x3674
+#define HIVE_SIZE_sp_frame_ptr_plane_r 4
+#endif
+
+/* function copy_frame_entry: 2CD */
+#ifdef HIVE_ADDR_copy_frame_entry
+#error Symbol copy_frame_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_copy_frame_entry 0x2CD
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_u) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_u != 0x3678 || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_u != 4)
+#error Symbol sp_frame_ptr_yuv_16_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_u 0x3678
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_u 4
+#endif
+
+#if defined(HIVE_MEM_vtmp4) && \
+ (HIVE_ADDR_vtmp4 != 0x31E8 || \
+ HIVE_SIZE_vtmp4 != 512)
+#error Symbol vtmp4 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vtmp4 scalar_processor_dmem
+#define HIVE_ADDR_vtmp4 0x31E8
+#define HIVE_SIZE_vtmp4 512
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_y_prev != 0x367C || \
+ HIVE_SIZE_sp_frame_ptr_y_prev != 4)
+#error Symbol sp_frame_ptr_y_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_prev 0x367C
+#define HIVE_SIZE_sp_frame_ptr_y_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_isp_binary_id) && \
+ (HIVE_ADDR_sp_isp_binary_id != 0x33E8 || \
+ HIVE_SIZE_sp_isp_binary_id != 4)
+#error Symbol sp_isp_binary_id occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_isp_binary_id scalar_processor_dmem
+#define HIVE_ADDR_sp_isp_binary_id 0x33E8
+#define HIVE_SIZE_sp_isp_binary_id 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_uncomp_bpp) && \
+ (HIVE_ADDR_sp_mipi_uncomp_bpp != 0x33EC || \
+ HIVE_SIZE_sp_mipi_uncomp_bpp != 4)
+#error Symbol sp_mipi_uncomp_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_uncomp_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_uncomp_bpp 0x33EC
+#define HIVE_SIZE_sp_mipi_uncomp_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_b) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_b != 0x3680 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_b != 4)
+#error Symbol sp_frame_ptr_qplane_b occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_b scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_b 0x3680
+#define HIVE_SIZE_sp_frame_ptr_qplane_b 4
+#endif
+
+#if defined(HIVE_MEM_sp_bin_copy_out) && \
+ (HIVE_ADDR_sp_bin_copy_out != 0x33F0 || \
+ HIVE_SIZE_sp_bin_copy_out != 4)
+#error Symbol sp_bin_copy_out occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_bin_copy_out scalar_processor_dmem
+#define HIVE_ADDR_sp_bin_copy_out 0x33F0
+#define HIVE_SIZE_sp_bin_copy_out 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_r) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_r != 0x3684 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_r != 4)
+#error Symbol sp_frame_ptr_qplane_r occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_r scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_r 0x3684
+#define HIVE_SIZE_sp_frame_ptr_qplane_r 4
+#endif
+
+/* function copy_frame: 2D2 */
+#if defined(HIVE_MEM_sp_out_crop_pos_y) && \
+ (HIVE_ADDR_sp_out_crop_pos_y != 0x33F4 || \
+ HIVE_SIZE_sp_out_crop_pos_y != 4)
+#error Symbol sp_out_crop_pos_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_out_crop_pos_y scalar_processor_dmem
+#define HIVE_ADDR_sp_out_crop_pos_y 0x33F4
+#define HIVE_SIZE_sp_out_crop_pos_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_start_x) && \
+ (HIVE_ADDR_sp_overlay_start_x != 0x33F8 || \
+ HIVE_SIZE_sp_overlay_start_x != 4)
+#error Symbol sp_overlay_start_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_start_x scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_start_x 0x33F8
+#define HIVE_SIZE_sp_overlay_start_x 4
+#endif
+
+/* function isp_gdc_var_sp_main: 354E */
+#if defined(HIVE_MEM_sp_mipi_comp_bpp) && \
+ (HIVE_ADDR_sp_mipi_comp_bpp != 0x33FC || \
+ HIVE_SIZE_sp_mipi_comp_bpp != 4)
+#error Symbol sp_mipi_comp_bpp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_comp_bpp scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_comp_bpp 0x33FC
+#define HIVE_SIZE_sp_mipi_comp_bpp 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_u) && \
+ (HIVE_ADDR_sp_frame_ptr_u != 0x3688 || \
+ HIVE_SIZE_sp_frame_ptr_u != 4)
+#error Symbol sp_frame_ptr_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u 0x3688
+#define HIVE_SIZE_sp_frame_ptr_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_online) && \
+ (HIVE_ADDR_sp_online != 0x3400 || \
+ HIVE_SIZE_sp_online != 4)
+#error Symbol sp_online occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_online scalar_processor_dmem
+#define HIVE_ADDR_sp_online 0x3400
+#define HIVE_SIZE_sp_online 4
+#endif
+
+/* function program_input_circuit: D0 */
+#if defined(HIVE_MEM_sp_vfin_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfin_c_frame_simdwidth != 0x3404 || \
+ HIVE_SIZE_sp_vfin_c_frame_simdwidth != 4)
+#error Symbol sp_vfin_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfin_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfin_c_frame_simdwidth 0x3404
+#define HIVE_SIZE_sp_vfin_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_v_addr) && \
+ (HIVE_ADDR_sp_output_v_addr != 0x3408 || \
+ HIVE_SIZE_sp_output_v_addr != 4)
+#error Symbol sp_output_v_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_v_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_v_addr 0x3408
+#define HIVE_SIZE_sp_output_v_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_v_in) && \
+ (HIVE_ADDR_sp_frame_ptr_v_in != 0x368C || \
+ HIVE_SIZE_sp_frame_ptr_v_in != 4)
+#error Symbol sp_frame_ptr_v_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v_in 0x368C
+#define HIVE_SIZE_sp_frame_ptr_v_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_y) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_y != 0x3690 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_y != 4)
+#error Symbol sp_frame_ptr_overlay_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_y 0x3690
+#define HIVE_SIZE_sp_frame_ptr_overlay_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_cropped_dimy) && \
+ (HIVE_ADDR_sp_frame_cropped_dimy != 0x340C || \
+ HIVE_SIZE_sp_frame_cropped_dimy != 4)
+#error Symbol sp_frame_cropped_dimy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_cropped_dimy scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_cropped_dimy 0x340C
+#define HIVE_SIZE_sp_frame_cropped_dimy 4
+#endif
+
+/* function sp_start_isp_entry: 0 */
+#ifdef HIVE_ADDR_sp_start_isp_entry
+#error Symbol sp_start_isp_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_start_isp_entry 0x0
+#endif
+
+#if defined(HIVE_MEM_sp_vfin_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfin_y_frame_simdwidth != 0x3410 || \
+ HIVE_SIZE_sp_vfin_y_frame_simdwidth != 4)
+#error Symbol sp_vfin_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfin_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfin_y_frame_simdwidth 0x3410
+#define HIVE_SIZE_sp_vfin_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_v) && \
+ (HIVE_ADDR_sp_si_bg_v != 0x3694 || \
+ HIVE_SIZE_sp_si_bg_v != 4)
+#error Symbol sp_si_bg_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_v 0x3694
+#define HIVE_SIZE_sp_si_bg_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_current_isp_program) && \
+ (HIVE_ADDR_sp_current_isp_program != 0x3174 || \
+ HIVE_SIZE_sp_current_isp_program != 4)
+#error Symbol sp_current_isp_program occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_current_isp_program scalar_processor_dmem
+#define HIVE_ADDR_sp_current_isp_program 0x3174
+#define HIVE_SIZE_sp_current_isp_program 4
+#endif
+
+/* function super_impose_offline_entry: 543 */
+#ifdef HIVE_ADDR_super_impose_offline_entry
+#error Symbol super_impose_offline_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_super_impose_offline_entry 0x543
+#endif
+
+#if defined(HIVE_MEM_sp_uds_chunk_cnt_y) && \
+ (HIVE_ADDR_sp_uds_chunk_cnt_y != 0x3698 || \
+ HIVE_SIZE_sp_uds_chunk_cnt_y != 4)
+#error Symbol sp_uds_chunk_cnt_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_chunk_cnt_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_chunk_cnt_y 0x3698
+#define HIVE_SIZE_sp_uds_chunk_cnt_y 4
+#endif
+
+/* function start_input: B5 */
+/* function sp_bin_copy: 255 */
+/* function sp_dma_proxy_configure_channel: D64 */
+/* function sp_gen_histogram_entry: 420 */
+#ifdef HIVE_ADDR_sp_gen_histogram_entry
+#error Symbol sp_gen_histogram_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_gen_histogram_entry 0x420
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_in) && \
+ (HIVE_ADDR_sp_frame_ptr_y_in != 0x369C || \
+ HIVE_SIZE_sp_frame_ptr_y_in != 4)
+#error Symbol sp_frame_ptr_y_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_in 0x369C
+#define HIVE_SIZE_sp_frame_ptr_y_in 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_y_addr) && \
+ (HIVE_ADDR_sp_input_y_addr != 0x3414 || \
+ HIVE_SIZE_sp_input_y_addr != 4)
+#error Symbol sp_input_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_y_addr 0x3414
+#define HIVE_SIZE_sp_input_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_sdis_horicoef_vectors) && \
+ (HIVE_ADDR_sp_sdis_horicoef_vectors != 0x3418 || \
+ HIVE_SIZE_sp_sdis_horicoef_vectors != 4)
+#error Symbol sp_sdis_horicoef_vectors occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sdis_horicoef_vectors scalar_processor_dmem
+#define HIVE_ADDR_sp_sdis_horicoef_vectors 0x3418
+#define HIVE_SIZE_sp_sdis_horicoef_vectors 4
+#endif
+
+#if defined(HIVE_MEM_sp_obarea_startBQ) && \
+ (HIVE_ADDR_sp_obarea_startBQ != 0x341C || \
+ HIVE_SIZE_sp_obarea_startBQ != 4)
+#error Symbol sp_obarea_startBQ occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_obarea_startBQ scalar_processor_dmem
+#define HIVE_ADDR_sp_obarea_startBQ 0x341C
+#define HIVE_SIZE_sp_obarea_startBQ 4
+#endif
+
+#if defined(HIVE_MEM_sp_g_dma_vtmp) && \
+ (HIVE_ADDR_sp_g_dma_vtmp != 0x36A0 || \
+ HIVE_SIZE_sp_g_dma_vtmp != 128)
+#error Symbol sp_g_dma_vtmp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_g_dma_vtmp scalar_processor_dmem
+#define HIVE_ADDR_sp_g_dma_vtmp 0x36A0
+#define HIVE_SIZE_sp_g_dma_vtmp 128
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_left_padding) && \
+ (HIVE_ADDR_sp_if_a_left_padding != 0x3720 || \
+ HIVE_SIZE_sp_if_a_left_padding != 4)
+#error Symbol sp_if_a_left_padding occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_left_padding scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_left_padding 0x3720
+#define HIVE_SIZE_sp_if_a_left_padding 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_vfout_y) && \
+ (HIVE_ADDR_sp_frame_ptr_vfout_y != 0x3724 || \
+ HIVE_SIZE_sp_frame_ptr_vfout_y != 4)
+#error Symbol sp_frame_ptr_vfout_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_vfout_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_vfout_y 0x3724
+#define HIVE_SIZE_sp_frame_ptr_vfout_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_timeout) && \
+ (HIVE_ADDR_sp_mipi_timeout != 0x3420 || \
+ HIVE_SIZE_sp_mipi_timeout != 4)
+#error Symbol sp_mipi_timeout occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_timeout scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_timeout 0x3420
+#define HIVE_SIZE_sp_mipi_timeout 4
+#endif
+
+/* function isp_video_offline_sp_main: 26B2 */
+#if defined(HIVE_MEM_sp_uds_ibuf_offset_y) && \
+ (HIVE_ADDR_sp_uds_ibuf_offset_y != 0x3728 || \
+ HIVE_SIZE_sp_uds_ibuf_offset_y != 44)
+#error Symbol sp_uds_ibuf_offset_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ibuf_offset_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ibuf_offset_y 0x3728
+#define HIVE_SIZE_sp_uds_ibuf_offset_y 44
+#endif
+
+#if defined(HIVE_MEM_sp_uds_ipx_start_array_u) && \
+ (HIVE_ADDR_sp_uds_ipx_start_array_u != 0x3754 || \
+ HIVE_SIZE_sp_uds_ipx_start_array_u != 44)
+#error Symbol sp_uds_ipx_start_array_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ipx_start_array_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ipx_start_array_u 0x3754
+#define HIVE_SIZE_sp_uds_ipx_start_array_u 44
+#endif
+
+/* function initialize_isp_xmem_base_addr_pointers: EB9 */
+#if defined(HIVE_MEM_sp_si_overlay_height) && \
+ (HIVE_ADDR_sp_si_overlay_height != 0x3780 || \
+ HIVE_SIZE_sp_si_overlay_height != 4)
+#error Symbol sp_si_overlay_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_height scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_height 0x3780
+#define HIVE_SIZE_sp_si_overlay_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_v) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_v != 0x3784 || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_v != 4)
+#error Symbol sp_frame_ptr_yuv_16_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_v 0x3784
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_y_delta) && \
+ (HIVE_ADDR_sp_tpg_y_delta != 0x3424 || \
+ HIVE_SIZE_sp_tpg_y_delta != 4)
+#error Symbol sp_tpg_y_delta occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_y_delta scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_y_delta 0x3424
+#define HIVE_SIZE_sp_tpg_y_delta 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_output_y_frame_simdwidth != 0x3428 || \
+ HIVE_SIZE_sp_output_y_frame_simdwidth != 4)
+#error Symbol sp_output_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_output_y_frame_simdwidth 0x3428
+#define HIVE_SIZE_sp_output_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_output_c_frame_simdwidth != 0x342C || \
+ HIVE_SIZE_sp_output_c_frame_simdwidth != 4)
+#error Symbol sp_output_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_output_c_frame_simdwidth 0x342C
+#define HIVE_SIZE_sp_output_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_shift) && \
+ (HIVE_ADDR_sp_si_blend_shift != 0x3788 || \
+ HIVE_SIZE_sp_si_blend_shift != 4)
+#error Symbol sp_si_blend_shift occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_shift scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_shift 0x3788
+#define HIVE_SIZE_sp_si_blend_shift 4
+#endif
+
+#if defined(HIVE_MEM__hrt_isp_css_curr_ch_id_sp) && \
+ (HIVE_ADDR__hrt_isp_css_curr_ch_id_sp != 0x3430 || \
+ HIVE_SIZE__hrt_isp_css_curr_ch_id_sp != 4)
+#error Symbol _hrt_isp_css_curr_ch_id_sp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM__hrt_isp_css_curr_ch_id_sp scalar_processor_dmem
+#define HIVE_ADDR__hrt_isp_css_curr_ch_id_sp 0x3430
+#define HIVE_SIZE__hrt_isp_css_curr_ch_id_sp 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_vecs) && \
+ (HIVE_ADDR_sp_if_a_buf_vecs != 0x378C || \
+ HIVE_SIZE_sp_if_a_buf_vecs != 4)
+#error Symbol sp_if_a_buf_vecs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_vecs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_vecs 0x378C
+#define HIVE_SIZE_sp_if_a_buf_vecs 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_width) && \
+ (HIVE_ADDR_sp_overlay_width != 0x3434 || \
+ HIVE_SIZE_sp_overlay_width != 4)
+#error Symbol sp_overlay_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_width scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_width 0x3434
+#define HIVE_SIZE_sp_overlay_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_vfout_y_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfout_y_frame_simdwidth != 0x3438 || \
+ HIVE_SIZE_sp_vfout_y_frame_simdwidth != 4)
+#error Symbol sp_vfout_y_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfout_y_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfout_y_frame_simdwidth 0x3438
+#define HIVE_SIZE_sp_vfout_y_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_mode) && \
+ (HIVE_ADDR_sp_input_mode != 0x343C || \
+ HIVE_SIZE_sp_input_mode != 4)
+#error Symbol sp_input_mode occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_mode scalar_processor_dmem
+#define HIVE_ADDR_sp_input_mode 0x343C
+#define HIVE_SIZE_sp_input_mode 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_xy_mask) && \
+ (HIVE_ADDR_sp_tpg_xy_mask != 0x3440 || \
+ HIVE_SIZE_sp_tpg_xy_mask != 4)
+#error Symbol sp_tpg_xy_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_xy_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_xy_mask 0x3440
+#define HIVE_SIZE_sp_tpg_xy_mask 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_width) && \
+ (HIVE_ADDR_sp_frame_width != 0x3444 || \
+ HIVE_SIZE_sp_frame_width != 4)
+#error Symbol sp_frame_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_width scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_width 0x3444
+#define HIVE_SIZE_sp_frame_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_vfout_c_frame_simdwidth) && \
+ (HIVE_ADDR_sp_vfout_c_frame_simdwidth != 0x3448 || \
+ HIVE_SIZE_sp_vfout_c_frame_simdwidth != 4)
+#error Symbol sp_vfout_c_frame_simdwidth occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vfout_c_frame_simdwidth scalar_processor_dmem
+#define HIVE_ADDR_sp_vfout_c_frame_simdwidth 0x3448
+#define HIVE_SIZE_sp_vfout_c_frame_simdwidth 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_start_y) && \
+ (HIVE_ADDR_sp_overlay_start_y != 0x344C || \
+ HIVE_SIZE_sp_overlay_start_y != 4)
+#error Symbol sp_overlay_start_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_start_y scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_start_y 0x344C
+#define HIVE_SIZE_sp_overlay_start_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_vf_crop_pos_y) && \
+ (HIVE_ADDR_sp_vf_crop_pos_y != 0x3450 || \
+ HIVE_SIZE_sp_vf_crop_pos_y != 4)
+#error Symbol sp_vf_crop_pos_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vf_crop_pos_y scalar_processor_dmem
+#define HIVE_ADDR_sp_vf_crop_pos_y 0x3450
+#define HIVE_SIZE_sp_vf_crop_pos_y 4
+#endif
+
+#if defined(HIVE_MEM_xmem_map_addr) && \
+ (HIVE_ADDR_xmem_map_addr != 0x3454 || \
+ HIVE_SIZE_xmem_map_addr != 4)
+#error Symbol xmem_map_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_xmem_map_addr scalar_processor_dmem
+#define HIVE_ADDR_xmem_map_addr 0x3454
+#define HIVE_SIZE_xmem_map_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_increment) && \
+ (HIVE_ADDR_sp_if_a_buf_increment != 0x3790 || \
+ HIVE_SIZE_sp_if_a_buf_increment != 4)
+#error Symbol sp_if_a_buf_increment occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_increment scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_increment 0x3790
+#define HIVE_SIZE_sp_if_a_buf_increment 4
+#endif
+
+#if defined(HIVE_MEM_sp_out_crop_pos_x) && \
+ (HIVE_ADDR_sp_out_crop_pos_x != 0x3458 || \
+ HIVE_SIZE_sp_out_crop_pos_x != 4)
+#error Symbol sp_out_crop_pos_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_out_crop_pos_x scalar_processor_dmem
+#define HIVE_ADDR_sp_out_crop_pos_x 0x3458
+#define HIVE_SIZE_sp_out_crop_pos_x 4
+#endif
+
+#if defined(HIVE_MEM___exit_value) && \
+ (HIVE_ADDR___exit_value != 0x0 || \
+ HIVE_SIZE___exit_value != 4)
+#error Symbol __exit_value occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM___exit_value scalar_processor_dmem
+#define HIVE_ADDR___exit_value 0x0
+#define HIVE_SIZE___exit_value 4
+#endif
+
+/* function isp_primary_var_sp_main: 1602 */
+/* function sp_gen_histogram: 425 */
+#if defined(HIVE_MEM_sp_output_y_addr) && \
+ (HIVE_ADDR_sp_output_y_addr != 0x345C || \
+ HIVE_SIZE_sp_output_y_addr != 4)
+#error Symbol sp_output_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_y_addr 0x345C
+#define HIVE_SIZE_sp_output_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_cropped_dimx) && \
+ (HIVE_ADDR_sp_frame_cropped_dimx != 0x3460 || \
+ HIVE_SIZE_sp_frame_cropped_dimx != 4)
+#error Symbol sp_frame_cropped_dimx occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_cropped_dimx scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_cropped_dimx 0x3460
+#define HIVE_SIZE_sp_frame_cropped_dimx 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_width) && \
+ (HIVE_ADDR_sp_si_overlay_width != 0x3794 || \
+ HIVE_SIZE_sp_si_overlay_width != 4)
+#error Symbol sp_si_overlay_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_width scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_width 0x3794
+#define HIVE_SIZE_sp_si_overlay_width 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_start_line) && \
+ (HIVE_ADDR_sp_if_a_start_line != 0x3798 || \
+ HIVE_SIZE_sp_if_a_start_line != 4)
+#error Symbol sp_if_a_start_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_start_line scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_start_line 0x3798
+#define HIVE_SIZE_sp_if_a_start_line 4
+#endif
+
+#if defined(HIVE_MEM_bayer_conf) && \
+ (HIVE_ADDR_bayer_conf != 0x138 || \
+ HIVE_SIZE_bayer_conf != 56)
+#error Symbol bayer_conf occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_bayer_conf scalar_processor_dmem
+#define HIVE_ADDR_bayer_conf 0x138
+#define HIVE_SIZE_bayer_conf 56
+#endif
+
+/* function sp_dma_proxy_write: CB0 */
+#if defined(HIVE_MEM_sp_if_block_fifo_no_reqs) && \
+ (HIVE_ADDR_sp_if_block_fifo_no_reqs != 0x379C || \
+ HIVE_SIZE_sp_if_block_fifo_no_reqs != 4)
+#error Symbol sp_if_block_fifo_no_reqs occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_block_fifo_no_reqs scalar_processor_dmem
+#define HIVE_ADDR_sp_if_block_fifo_no_reqs 0x379C
+#define HIVE_SIZE_sp_if_block_fifo_no_reqs 4
+#endif
+
+#if defined(HIVE_MEM_sp_sync_gen_hblank_cycles) && \
+ (HIVE_ADDR_sp_sync_gen_hblank_cycles != 0x3464 || \
+ HIVE_SIZE_sp_sync_gen_hblank_cycles != 4)
+#error Symbol sp_sync_gen_hblank_cycles occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_hblank_cycles scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_hblank_cycles 0x3464
+#define HIVE_SIZE_sp_sync_gen_hblank_cycles 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_last_u) && \
+ (HIVE_ADDR_sp_uds_oxdim_last_u != 0x37A0 || \
+ HIVE_SIZE_sp_uds_oxdim_last_u != 4)
+#error Symbol sp_uds_oxdim_last_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_last_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_last_u 0x37A0
+#define HIVE_SIZE_sp_uds_oxdim_last_u 4
+#endif
+
+/* function stop_input: 9A */
+#if defined(HIVE_MEM_sp_frame_ptr_u_in) && \
+ (HIVE_ADDR_sp_frame_ptr_u_in != 0x37A4 || \
+ HIVE_SIZE_sp_frame_ptr_u_in != 4)
+#error Symbol sp_frame_ptr_u_in occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u_in scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u_in 0x37A4
+#define HIVE_SIZE_sp_frame_ptr_u_in 4
+#endif
+
+/* function isp_vf_pp_sp_main: FBE */
+#if defined(HIVE_MEM_sp_sync_gen_height) && \
+ (HIVE_ADDR_sp_sync_gen_height != 0x3468 || \
+ HIVE_SIZE_sp_sync_gen_height != 4)
+#error Symbol sp_sync_gen_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_sync_gen_height scalar_processor_dmem
+#define HIVE_ADDR_sp_sync_gen_height 0x3468
+#define HIVE_SIZE_sp_sync_gen_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_program_input_circuit) && \
+ (HIVE_ADDR_sp_program_input_circuit != 0x346C || \
+ HIVE_SIZE_sp_program_input_circuit != 4)
+#error Symbol sp_program_input_circuit occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_program_input_circuit scalar_processor_dmem
+#define HIVE_ADDR_sp_program_input_circuit 0x346C
+#define HIVE_SIZE_sp_program_input_circuit 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_start_column) && \
+ (HIVE_ADDR_sp_if_a_start_column != 0x37A8 || \
+ HIVE_SIZE_sp_if_a_start_column != 4)
+#error Symbol sp_if_a_start_column occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_start_column scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_start_column 0x37A8
+#define HIVE_SIZE_sp_if_a_start_column 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_changed) && \
+ (HIVE_ADDR_sp_if_b_changed != 0x37AC || \
+ HIVE_SIZE_sp_if_b_changed != 4)
+#error Symbol sp_if_b_changed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_changed scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_changed 0x37AC
+#define HIVE_SIZE_sp_if_b_changed 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_y) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_y != 0x37B0 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_y != 4)
+#error Symbol sp_uds_dma_pixel_block_width_a_in_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_y 0x37B0
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_y 4
+#endif
+
+/* function isp_primary_16mp_sp_main: 1181 */
+#if defined(HIVE_MEM_sp_uds_ibuf_offset_u) && \
+ (HIVE_ADDR_sp_uds_ibuf_offset_u != 0x37B4 || \
+ HIVE_SIZE_sp_uds_ibuf_offset_u != 44)
+#error Symbol sp_uds_ibuf_offset_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ibuf_offset_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ibuf_offset_u 0x37B4
+#define HIVE_SIZE_sp_uds_ibuf_offset_u 44
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_qplane_gr) && \
+ (HIVE_ADDR_sp_frame_ptr_qplane_gr != 0x37E0 || \
+ HIVE_SIZE_sp_frame_ptr_qplane_gr != 4)
+#error Symbol sp_frame_ptr_qplane_gr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_qplane_gr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_qplane_gr 0x37E0
+#define HIVE_SIZE_sp_frame_ptr_qplane_gr 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_bg_v) && \
+ (HIVE_ADDR_sp_overlay_bg_v != 0x3470 || \
+ HIVE_SIZE_sp_overlay_bg_v != 4)
+#error Symbol sp_overlay_bg_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_v scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_v 0x3470
+#define HIVE_SIZE_sp_overlay_bg_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_deinterleaving) && \
+ (HIVE_ADDR_sp_if_b_deinterleaving != 0x37E4 || \
+ HIVE_SIZE_sp_if_b_deinterleaving != 4)
+#error Symbol sp_if_b_deinterleaving occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_deinterleaving scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_deinterleaving 0x37E4
+#define HIVE_SIZE_sp_if_b_deinterleaving 4
+#endif
+
+#if defined(HIVE_MEM_sp_output_u_addr) && \
+ (HIVE_ADDR_sp_output_u_addr != 0x3474 || \
+ HIVE_SIZE_sp_output_u_addr != 4)
+#error Symbol sp_output_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_output_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_output_u_addr 0x3474
+#define HIVE_SIZE_sp_output_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_v) && \
+ (HIVE_ADDR_sp_si_blend_input_v != 0x37E8 || \
+ HIVE_SIZE_sp_si_blend_input_v != 4)
+#error Symbol sp_si_blend_input_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_v scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_v 0x37E8
+#define HIVE_SIZE_sp_si_blend_input_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_vectors_per_line) && \
+ (HIVE_ADDR_sp_vectors_per_line != 0x3478 || \
+ HIVE_SIZE_sp_vectors_per_line != 4)
+#error Symbol sp_vectors_per_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vectors_per_line scalar_processor_dmem
+#define HIVE_ADDR_sp_vectors_per_line 0x3478
+#define HIVE_SIZE_sp_vectors_per_line 4
+#endif
+
+/* function _initialize_ispparm_from_host: F9E */
+#if defined(HIVE_MEM_sp_if_b_start_column) && \
+ (HIVE_ADDR_sp_if_b_start_column != 0x37EC || \
+ HIVE_SIZE_sp_if_b_start_column != 4)
+#error Symbol sp_if_b_start_column occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_start_column scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_start_column 0x37EC
+#define HIVE_SIZE_sp_if_b_start_column 4
+#endif
+
+/* function init_ifs: DA7 */
+/* function super_impose_offline: 548 */
+#if defined(HIVE_MEM_sp_init_isp) && \
+ (HIVE_ADDR_sp_init_isp != 0x347C || \
+ HIVE_SIZE_sp_init_isp != 4)
+#error Symbol sp_init_isp occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_init_isp scalar_processor_dmem
+#define HIVE_ADDR_sp_init_isp 0x347C
+#define HIVE_SIZE_sp_init_isp 4
+#endif
+
+/* function hrt_isp_css_sp_store_isp_data: 3C04 */
+#if defined(HIVE_MEM_sp_if_b_buf_start_index) && \
+ (HIVE_ADDR_sp_if_b_buf_start_index != 0x37F0 || \
+ HIVE_SIZE_sp_if_b_buf_start_index != 4)
+#error Symbol sp_if_b_buf_start_index occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_start_index scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_start_index 0x37F0
+#define HIVE_SIZE_sp_if_b_buf_start_index 4
+#endif
+
+#if defined(HIVE_MEM_bits_per_pixel) && \
+ (HIVE_ADDR_bits_per_pixel != 0x3480 || \
+ HIVE_SIZE_bits_per_pixel != 4)
+#error Symbol bits_per_pixel occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_bits_per_pixel scalar_processor_dmem
+#define HIVE_ADDR_bits_per_pixel 0x3480
+#define HIVE_SIZE_bits_per_pixel 4
+#endif
+
+#if defined(HIVE_MEM_output_image_format) && \
+ (HIVE_ADDR_output_image_format != 0x3484 || \
+ HIVE_SIZE_output_image_format != 4)
+#error Symbol output_image_format occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_output_image_format scalar_processor_dmem
+#define HIVE_ADDR_output_image_format 0x3484
+#define HIVE_SIZE_output_image_format 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_height) && \
+ (HIVE_ADDR_sp_frame_height != 0x3488 || \
+ HIVE_SIZE_sp_frame_height != 4)
+#error Symbol sp_frame_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_height scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_height 0x3488
+#define HIVE_SIZE_sp_frame_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_chunk_cnt_u) && \
+ (HIVE_ADDR_sp_uds_chunk_cnt_u != 0x37F4 || \
+ HIVE_SIZE_sp_uds_chunk_cnt_u != 4)
+#error Symbol sp_uds_chunk_cnt_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_chunk_cnt_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_chunk_cnt_u 0x37F4
+#define HIVE_SIZE_sp_uds_chunk_cnt_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_bg_y) && \
+ (HIVE_ADDR_sp_si_bg_y != 0x37F8 || \
+ HIVE_SIZE_sp_si_bg_y != 4)
+#error Symbol sp_si_bg_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_bg_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_bg_y 0x37F8
+#define HIVE_SIZE_sp_si_bg_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_buf_increment) && \
+ (HIVE_ADDR_sp_if_b_buf_increment != 0x37FC || \
+ HIVE_SIZE_sp_if_b_buf_increment != 4)
+#error Symbol sp_if_b_buf_increment occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_buf_increment scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_buf_increment 0x37FC
+#define HIVE_SIZE_sp_if_b_buf_increment 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_deinterleaving) && \
+ (HIVE_ADDR_sp_if_a_deinterleaving != 0x3800 || \
+ HIVE_SIZE_sp_if_a_deinterleaving != 4)
+#error Symbol sp_if_a_deinterleaving occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_deinterleaving scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_deinterleaving 0x3800
+#define HIVE_SIZE_sp_if_a_deinterleaving 4
+#endif
+
+/* function sp_dma_proxy_init: C47 */
+#if defined(HIVE_MEM_sp_uds_dy) && \
+ (HIVE_ADDR_sp_uds_dy != 0x3804 || \
+ HIVE_SIZE_sp_uds_dy != 4)
+#error Symbol sp_uds_dy occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dy scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dy 0x3804
+#define HIVE_SIZE_sp_uds_dy 4
+#endif
+
+/* function _init_frame_pointers: E13 */
+#if defined(HIVE_MEM_sp_overlay_bg_y) && \
+ (HIVE_ADDR_sp_overlay_bg_y != 0x348C || \
+ HIVE_SIZE_sp_overlay_bg_y != 4)
+#error Symbol sp_overlay_bg_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_bg_y scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_bg_y 0x348C
+#define HIVE_SIZE_sp_overlay_bg_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_histo_addr) && \
+ (HIVE_ADDR_sp_histo_addr != 0x3490 || \
+ HIVE_SIZE_sp_histo_addr != 4)
+#error Symbol sp_histo_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_histo_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_histo_addr 0x3490
+#define HIVE_SIZE_sp_histo_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_u_addr) && \
+ (HIVE_ADDR_sp_overlay_u_addr != 0x3494 || \
+ HIVE_SIZE_sp_overlay_u_addr != 4)
+#error Symbol sp_overlay_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_u_addr 0x3494
+#define HIVE_SIZE_sp_overlay_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_uv_tnr) && \
+ (HIVE_ADDR_sp_frame_ptr_uv_tnr != 0x3808 || \
+ HIVE_SIZE_sp_frame_ptr_uv_tnr != 4)
+#error Symbol sp_frame_ptr_uv_tnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_uv_tnr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_uv_tnr 0x3808
+#define HIVE_SIZE_sp_frame_ptr_uv_tnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_input_u_addr) && \
+ (HIVE_ADDR_sp_input_u_addr != 0x3498 || \
+ HIVE_SIZE_sp_input_u_addr != 4)
+#error Symbol sp_input_u_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_input_u_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_input_u_addr 0x3498
+#define HIVE_SIZE_sp_input_u_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_buf_eol_offset) && \
+ (HIVE_ADDR_sp_if_a_buf_eol_offset != 0x380C || \
+ HIVE_SIZE_sp_if_a_buf_eol_offset != 4)
+#error Symbol sp_if_a_buf_eol_offset occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_buf_eol_offset scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_buf_eol_offset 0x380C
+#define HIVE_SIZE_sp_if_a_buf_eol_offset 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_raw) && \
+ (HIVE_ADDR_sp_frame_ptr_raw != 0x3810 || \
+ HIVE_SIZE_sp_frame_ptr_raw != 4)
+#error Symbol sp_frame_ptr_raw occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_raw scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_raw 0x3810
+#define HIVE_SIZE_sp_frame_ptr_raw 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_u) && \
+ (HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_u != 0x3814 || \
+ HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_u != 4)
+#error Symbol sp_uds_dma_pixel_block_width_a_in_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dma_pixel_block_width_a_in_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dma_pixel_block_width_a_in_u 0x3814
+#define HIVE_SIZE_sp_uds_dma_pixel_block_width_a_in_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y) && \
+ (HIVE_ADDR_sp_frame_ptr_y != 0x3818 || \
+ HIVE_SIZE_sp_frame_ptr_y != 4)
+#error Symbol sp_frame_ptr_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y 0x3818
+#define HIVE_SIZE_sp_frame_ptr_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_tpg_y_mask) && \
+ (HIVE_ADDR_sp_tpg_y_mask != 0x349C || \
+ HIVE_SIZE_sp_tpg_y_mask != 4)
+#error Symbol sp_tpg_y_mask occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_tpg_y_mask scalar_processor_dmem
+#define HIVE_ADDR_sp_tpg_y_mask 0x349C
+#define HIVE_SIZE_sp_tpg_y_mask 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woix_last_u) && \
+ (HIVE_ADDR_sp_uds_woix_last_u != 0x381C || \
+ HIVE_SIZE_sp_uds_woix_last_u != 4)
+#error Symbol sp_uds_woix_last_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix_last_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix_last_u 0x381C
+#define HIVE_SIZE_sp_uds_woix_last_u 4
+#endif
+
+/* function isp_preview_var_sp_main: 2073 */
+#if defined(HIVE_MEM_sp_uds_dx) && \
+ (HIVE_ADDR_sp_uds_dx != 0x3820 || \
+ HIVE_SIZE_sp_uds_dx != 4)
+#error Symbol sp_uds_dx occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_dx scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_dx 0x3820
+#define HIVE_SIZE_sp_uds_dx 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_y_tnr) && \
+ (HIVE_ADDR_sp_frame_ptr_y_tnr != 0x3824 || \
+ HIVE_SIZE_sp_frame_ptr_y_tnr != 4)
+#error Symbol sp_frame_ptr_y_tnr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_y_tnr scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_y_tnr 0x3824
+#define HIVE_SIZE_sp_frame_ptr_y_tnr 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_u_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_u_prev != 0x3828 || \
+ HIVE_SIZE_sp_frame_ptr_u_prev != 4)
+#error Symbol sp_frame_ptr_u_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_u_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_u_prev 0x3828
+#define HIVE_SIZE_sp_frame_ptr_u_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_cropped_height) && \
+ (HIVE_ADDR_sp_if_b_cropped_height != 0x382C || \
+ HIVE_SIZE_sp_if_b_cropped_height != 4)
+#error Symbol sp_if_b_cropped_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_cropped_height scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_cropped_height 0x382C
+#define HIVE_SIZE_sp_if_b_cropped_height 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_woix_last_y) && \
+ (HIVE_ADDR_sp_uds_woix_last_y != 0x3830 || \
+ HIVE_SIZE_sp_uds_woix_last_y != 4)
+#error Symbol sp_uds_woix_last_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_woix_last_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_woix_last_y 0x3830
+#define HIVE_SIZE_sp_uds_woix_last_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_g_macc_coef) && \
+ (HIVE_ADDR_sp_g_macc_coef != 0x3834 || \
+ HIVE_SIZE_sp_g_macc_coef != 512)
+#error Symbol sp_g_macc_coef occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_g_macc_coef scalar_processor_dmem
+#define HIVE_ADDR_sp_g_macc_coef 0x3834
+#define HIVE_SIZE_sp_g_macc_coef 512
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_ratb) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_ratb != 0x3A34 || \
+ HIVE_SIZE_sp_frame_ptr_plane_ratb != 4)
+#error Symbol sp_frame_ptr_plane_ratb occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_ratb scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_ratb 0x3A34
+#define HIVE_SIZE_sp_frame_ptr_plane_ratb 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_start_y) && \
+ (HIVE_ADDR_sp_si_overlay_start_y != 0x3A38 || \
+ HIVE_SIZE_sp_si_overlay_start_y != 4)
+#error Symbol sp_si_overlay_start_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_start_y scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_start_y 0x3A38
+#define HIVE_SIZE_sp_si_overlay_start_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_yuv_16_y) && \
+ (HIVE_ADDR_sp_frame_ptr_yuv_16_y != 0x3A3C || \
+ HIVE_SIZE_sp_frame_ptr_yuv_16_y != 4)
+#error Symbol sp_frame_ptr_yuv_16_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_yuv_16_y scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_yuv_16_y 0x3A3C
+#define HIVE_SIZE_sp_frame_ptr_yuv_16_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_debug) && \
+ (HIVE_ADDR_sp_debug != 0x353C || \
+ HIVE_SIZE_sp_debug != 64)
+#error Symbol sp_debug occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_debug scalar_processor_dmem
+#define HIVE_ADDR_sp_debug 0x353C
+#define HIVE_SIZE_sp_debug 64
+#endif
+
+/* function isp_primary_small_sp_main: 19F7 */
+#if defined(HIVE_MEM_sp_frame_ptr_v_prev) && \
+ (HIVE_ADDR_sp_frame_ptr_v_prev != 0x3A40 || \
+ HIVE_SIZE_sp_frame_ptr_v_prev != 4)
+#error Symbol sp_frame_ptr_v_prev occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_v_prev scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_v_prev 0x3A40
+#define HIVE_SIZE_sp_frame_ptr_v_prev 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_y_addr) && \
+ (HIVE_ADDR_sp_overlay_y_addr != 0x34A0 || \
+ HIVE_SIZE_sp_overlay_y_addr != 4)
+#error Symbol sp_overlay_y_addr occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_y_addr scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_y_addr 0x34A0
+#define HIVE_SIZE_sp_overlay_y_addr 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_iy_topleft_y) && \
+ (HIVE_ADDR_sp_uds_iy_topleft_y != 0x3A44 || \
+ HIVE_SIZE_sp_uds_iy_topleft_y != 4)
+#error Symbol sp_uds_iy_topleft_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_iy_topleft_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_iy_topleft_y 0x3A44
+#define HIVE_SIZE_sp_uds_iy_topleft_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_mipi_port) && \
+ (HIVE_ADDR_sp_mipi_port != 0x34A4 || \
+ HIVE_SIZE_sp_mipi_port != 4)
+#error Symbol sp_mipi_port occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_mipi_port scalar_processor_dmem
+#define HIVE_ADDR_sp_mipi_port 0x34A4
+#define HIVE_SIZE_sp_mipi_port 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_start_line) && \
+ (HIVE_ADDR_sp_if_b_start_line != 0x3A48 || \
+ HIVE_SIZE_sp_if_b_start_line != 4)
+#error Symbol sp_if_b_start_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_start_line scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_start_line 0x3A48
+#define HIVE_SIZE_sp_if_b_start_line 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_blend_input_u) && \
+ (HIVE_ADDR_sp_si_blend_input_u != 0x3A4C || \
+ HIVE_SIZE_sp_si_blend_input_u != 4)
+#error Symbol sp_si_blend_input_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_blend_input_u scalar_processor_dmem
+#define HIVE_ADDR_sp_si_blend_input_u 0x3A4C
+#define HIVE_SIZE_sp_si_blend_input_u 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_overlay_v) && \
+ (HIVE_ADDR_sp_frame_ptr_overlay_v != 0x3A50 || \
+ HIVE_SIZE_sp_frame_ptr_overlay_v != 4)
+#error Symbol sp_frame_ptr_overlay_v occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_overlay_v scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_overlay_v 0x3A50
+#define HIVE_SIZE_sp_frame_ptr_overlay_v 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_floored_u) && \
+ (HIVE_ADDR_sp_uds_oxdim_floored_u != 0x3A54 || \
+ HIVE_SIZE_sp_uds_oxdim_floored_u != 4)
+#error Symbol sp_uds_oxdim_floored_u occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_floored_u scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_floored_u 0x3A54
+#define HIVE_SIZE_sp_uds_oxdim_floored_u 4
+#endif
+
+/* function isp_video_online_nodz_sp_main: 3072 */
+#if defined(HIVE_MEM_sp_vectors_per_input_line) && \
+ (HIVE_ADDR_sp_vectors_per_input_line != 0x34A8 || \
+ HIVE_SIZE_sp_vectors_per_input_line != 4)
+#error Symbol sp_vectors_per_input_line occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_vectors_per_input_line scalar_processor_dmem
+#define HIVE_ADDR_sp_vectors_per_input_line 0x34A8
+#define HIVE_SIZE_sp_vectors_per_input_line 4
+#endif
+
+#if defined(HIVE_MEM_sp_overlay_height) && \
+ (HIVE_ADDR_sp_overlay_height != 0x34AC || \
+ HIVE_SIZE_sp_overlay_height != 4)
+#error Symbol sp_overlay_height occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_overlay_height scalar_processor_dmem
+#define HIVE_ADDR_sp_overlay_height 0x34AC
+#define HIVE_SIZE_sp_overlay_height 4
+#endif
+
+#if defined(HIVE_MEM_dma_proxy_kill_req) && \
+ (HIVE_ADDR_dma_proxy_kill_req != 0x2C68 || \
+ HIVE_SIZE_dma_proxy_kill_req != 1)
+#error Symbol dma_proxy_kill_req occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_dma_proxy_kill_req scalar_processor_dmem
+#define HIVE_ADDR_dma_proxy_kill_req 0x2C68
+#define HIVE_SIZE_dma_proxy_kill_req 1
+#endif
+
+#if defined(HIVE_MEM_mem_map) && \
+ (HIVE_ADDR_mem_map != 0x3A58 || \
+ HIVE_SIZE_mem_map != 108)
+#error Symbol mem_map occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_mem_map scalar_processor_dmem
+#define HIVE_ADDR_mem_map 0x3A58
+#define HIVE_SIZE_mem_map 108
+#endif
+
+#if defined(HIVE_MEM_sp_if_a_changed) && \
+ (HIVE_ADDR_sp_if_a_changed != 0x3AC4 || \
+ HIVE_SIZE_sp_if_a_changed != 4)
+#error Symbol sp_if_a_changed occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_a_changed scalar_processor_dmem
+#define HIVE_ADDR_sp_if_a_changed 0x3AC4
+#define HIVE_SIZE_sp_if_a_changed 4
+#endif
+
+#if defined(HIVE_MEM_sp_frame_ptr_plane_b) && \
+ (HIVE_ADDR_sp_frame_ptr_plane_b != 0x3AC8 || \
+ HIVE_SIZE_sp_frame_ptr_plane_b != 4)
+#error Symbol sp_frame_ptr_plane_b occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_frame_ptr_plane_b scalar_processor_dmem
+#define HIVE_ADDR_sp_frame_ptr_plane_b 0x3AC8
+#define HIVE_SIZE_sp_frame_ptr_plane_b 4
+#endif
+
+#if defined(HIVE_MEM_sp_uds_oxdim_floored_y) && \
+ (HIVE_ADDR_sp_uds_oxdim_floored_y != 0x3ACC || \
+ HIVE_SIZE_sp_uds_oxdim_floored_y != 4)
+#error Symbol sp_uds_oxdim_floored_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_floored_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_floored_y 0x3ACC
+#define HIVE_SIZE_sp_uds_oxdim_floored_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_si_overlay_start_x) && \
+ (HIVE_ADDR_sp_si_overlay_start_x != 0x3AD0 || \
+ HIVE_SIZE_sp_si_overlay_start_x != 4)
+#error Symbol sp_si_overlay_start_x occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_si_overlay_start_x scalar_processor_dmem
+#define HIVE_ADDR_sp_si_overlay_start_x 0x3AD0
+#define HIVE_SIZE_sp_si_overlay_start_x 4
+#endif
+
+#if defined(HIVE_MEM_sp_if_b_cropped_width) && \
+ (HIVE_ADDR_sp_if_b_cropped_width != 0x3AD4 || \
+ HIVE_SIZE_sp_if_b_cropped_width != 4)
+#error Symbol sp_if_b_cropped_width occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_if_b_cropped_width scalar_processor_dmem
+#define HIVE_ADDR_sp_if_b_cropped_width 0x3AD4
+#define HIVE_SIZE_sp_if_b_cropped_width 4
+#endif
+
+#if defined(HIVE_MEM_vtmp1) && \
+ (HIVE_ADDR_vtmp1 != 0x34B0 || \
+ HIVE_SIZE_vtmp1 != 128)
+#error Symbol vtmp1 occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_vtmp1 scalar_processor_dmem
+#define HIVE_ADDR_vtmp1 0x34B0
+#define HIVE_SIZE_vtmp1 128
+#endif
+
+#if defined(HIVE_MEM_sp_uds_ipx_start_array_y) && \
+ (HIVE_ADDR_sp_uds_ipx_start_array_y != 0x3AD8 || \
+ HIVE_SIZE_sp_uds_ipx_start_array_y != 44)
+#error Symbol sp_uds_ipx_start_array_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_ipx_start_array_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_ipx_start_array_y 0x3AD8
+#define HIVE_SIZE_sp_uds_ipx_start_array_y 44
+#endif
+
+/* function isp_video_online_ds_sp_main: 2D0E */
+#if defined(HIVE_MEM_sp_uds_oxdim_last_y) && \
+ (HIVE_ADDR_sp_uds_oxdim_last_y != 0x3B04 || \
+ HIVE_SIZE_sp_uds_oxdim_last_y != 4)
+#error Symbol sp_uds_oxdim_last_y occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_uds_oxdim_last_y scalar_processor_dmem
+#define HIVE_ADDR_sp_uds_oxdim_last_y 0x3B04
+#define HIVE_SIZE_sp_uds_oxdim_last_y 4
+#endif
+
+#if defined(HIVE_MEM_sp_2ppc) && \
+ (HIVE_ADDR_sp_2ppc != 0x3530 || \
+ HIVE_SIZE_sp_2ppc != 4)
+#error Symbol sp_2ppc occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_MEM_sp_2ppc scalar_processor_dmem
+#define HIVE_ADDR_sp_2ppc 0x3530
+#define HIVE_SIZE_sp_2ppc 4
+#endif
+
+/* function sp_dma_proxy_run: 771 */
+/* function sp_bin_copy_entry: 250 */
+#ifdef HIVE_ADDR_sp_bin_copy_entry
+#error Symbol sp_bin_copy_entry occurs in multiple mapfiles, \
+please rename or split host code into separate modules
+#else
+#define HIVE_ADDR_sp_bin_copy_entry 0x250
+#endif
+
+#endif /* _SP_MAP_H_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/sp_hrt.h b/drivers/media/video/atomisp/include/css_hrt/sp_hrt.h
new file mode 100644
index 0000000..54b3be1
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/sp_hrt.h
@@ -0,0 +1,31 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _sp_hrt_h_
+#define _sp_hrt_h_
+
+#define hrt_sp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _dmem)
+
+#define hrt_sp_dmem_master_port_address(cell) \
+ hrt_mem_master_port_address(cell, hrt_sp_dmem(cell))
+
+#endif /* _sp_hrt_h_ */
diff --git a/drivers/media/video/atomisp/include/css_hrt/streaming_to_mipi_defs.h b/drivers/media/video/atomisp/include/css_hrt/streaming_to_mipi_defs.h
new file mode 100644
index 0000000..2cebd02
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/streaming_to_mipi_defs.h
@@ -0,0 +1,36 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _streaming_to_mipi_defs_h
+#define _streaming_to_mipi_defs_h
+
+#define HIVE_STR_TO_MIPI_VALID_A_BIT 0
+#define HIVE_STR_TO_MIPI_VALID_B_BIT 1
+#define HIVE_STR_TO_MIPI_SOL_BIT 2
+#define HIVE_STR_TO_MIPI_EOL_BIT 3
+#define HIVE_STR_TO_MIPI_SOF_BIT 4
+#define HIVE_STR_TO_MIPI_EOF_BIT 5
+#define HIVE_STR_TO_MIPI_CH_ID_LSB 6
+
+#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1)
+
+#endif /* _streaming_to_mipi_defs_h */
diff --git a/drivers/media/video/atomisp/include/css_hrt/vector.h b/drivers/media/video/atomisp/include/css_hrt/vector.h
new file mode 100644
index 0000000..5f3d0d9
--- /dev/null
+++ b/drivers/media/video/atomisp/include/css_hrt/vector.h
@@ -0,0 +1,110 @@
+/*
+ * Support for Medifield PNW Camera Imaging ISP subsystem.
+ *
+ * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
+ *
+ * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#ifndef _HRT_VECTOR_H_
+#define _HRT_VECTOR_H_
+
+/* This file contains support to convert between vectors represented
+ * as arrays of int (on the host) and real packed vectors on a target
+ * processor.
+ * It also contains functions to transfer these vectors between a host
+ * processor and a target (vector) processor.
+ * Note that this file is not to be included directly by application code,
+ * but only through a processor specific header file. The reason for this
+ * is this set of macros has to be defined for a given processor of type
+ * <proc_type>:
+ * <proc_type>_vector_alignment: the alignment in bytes of an entire
+ * vector in memory
+ * <proc_type>_vector_elem_bits: number of bits per vector element in
+ * memory
+ * <proc_type>_vector_elem_precision: number of valid bits per vector element,
+ * this can be smaller than the
+ * vector_elem_bits if the width of a
+ * vector element differs between the vector
+ * memory and the datapath
+ * <proc_type>_vector_num_elems: the number of elements per vector
+ */
+#include "bits.h"
+
+#define _hrt_vector_set_bit(a, b, c) ((a)|((b)<<(c)))
+
+#define _hrt_ceil_div(a, b) (((a)+(b)-1)/(b))
+#define _hrt_extend(a, bit) (((a)<<(32-bit))>>(32-bit))
+#define _hrt_sign_extend(a, bit) _hrt_extend((int)(a), (bit))
+#define _hrt_zero_extend(a, bit) _hrt_extend((unsigned)(a), (bit))
+
+static inline void
+_hrt_decode_vector(char *vec_in, int *vec_out, int elem_bits,
+ int elem_precision, int num_elems, int sign_extend)
+{
+ int i, j, ptr = 0, pos = 0;
+
+ for (i = 0; i < num_elems; i++) {
+ unsigned int value = 0;
+ for (j = 0; j < elem_bits; j++) {
+ unsigned int b = _hrt_get_bit(vec_in[ptr], pos);
+ value = _hrt_vector_set_bit(value, b, j);
+ pos++;
+ if (pos == 8) {
+ ptr++;
+ pos = 0;
+ }
+ }
+ if (sign_extend)
+ vec_out[i] = _hrt_sign_extend(value, elem_precision);
+ else
+ vec_out[i] = _hrt_zero_extend(value, elem_precision);
+ }
+}
+
+static inline void
+_hrt_encode_vector(int *vec_in, char *vec_out, int elem_bits,
+ int elem_precision, int num_elems, int sign_extend)
+{
+ unsigned char v = 0;
+ int i, j, ptr = 0, pos = 0;
+
+ for (i = 0; i < num_elems; i++) {
+ unsigned int value;
+ if (sign_extend)
+ value = _hrt_sign_extend(vec_in[i], elem_precision);
+ else
+ value = _hrt_zero_extend(vec_in[i], elem_precision);
+ for (j = 0; j < elem_bits; j++) {
+ unsigned int b = _hrt_get_bit(value, j);
+ v = _hrt_vector_set_bit(v, b, pos);
+ pos++;
+
+ if (pos == 8) {
+ vec_out[ptr++] = v;
+ pos = 0;
+ v = 0;
+ }
+ }
+ }
+ /* if we started writing a byte, but did not finish it, finish it here.
+ This happens when num_elems*elem_bits is not a multiple of 8 */
+ if (pos && pos != 8)
+ vec_out[ptr] = v;
+}
+
+#endif /* _HRT_VECTOR_H_ */
--
1.5.4.3
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