[Meego-kernel] [PATCH 13/15] Support for OverlayC and subpicture
hitesh.k.patel at intel.com
hitesh.k.patel at intel.com
Sun Oct 10 08:33:44 PDT 2010
From: Hitesh K. Patel <hitesh.k.patel at intel.com>
Patch from: Jason Hu <jason.hu at intel.com>
Add support for OverlayC and subpicture to Video driver.
Signed-off-by: Hitesh K. Patel <hitesh.k.patel at intel.com>
---
drivers/staging/mrst/drv/psb_drm.h | 10 +++
drivers/staging/mrst/drv/psb_drv.c | 92 ++++++++++++++++++++++++++++++
drivers/staging/mrst/drv/psb_drv.h | 7 ++
drivers/staging/mrst/drv/psb_intel_reg.h | 7 ++
4 files changed, 116 insertions(+), 0 deletions(-)
diff --git a/drivers/staging/mrst/drv/psb_drm.h b/drivers/staging/mrst/drv/psb_drm.h
index f5dc077..04c0738 100644
--- a/drivers/staging/mrst/drv/psb_drm.h
+++ b/drivers/staging/mrst/drv/psb_drm.h
@@ -521,10 +521,17 @@ struct drm_psb_stolen_memory_arg {
#ifdef MDFLD_HDCP
#define REGRWBITS_HDCP (1 << 7)
#endif
+#define REGRWBITS_DSPACNTR (1 << 8)
+#define REGRWBITS_DSPBCNTR (1 << 9)
+#define REGRWBITS_DSPCCNTR (1 << 10)
+
/*Overlay Register Bits*/
#define OV_REGRWBITS_OVADD (1 << 0)
#define OV_REGRWBITS_OGAM_ALL (1 << 1)
+#define OVC_REGRWBITS_OVADD (1 << 2)
+#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
+
struct drm_psb_register_rw_arg {
uint32_t b_force_hw_on;
@@ -575,6 +582,9 @@ struct drm_psb_register_rw_arg {
uint32_t dspc_size;
uint32_t dspc_surface;
} sprite;
+
+ uint32_t subpicture_enable_mask;
+ uint32_t subpicture_disable_mask;
};
struct psb_gtt_mapping_arg {
diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c
index b2dbddd..6d12774 100644
--- a/drivers/staging/mrst/drv/psb_drv.c
+++ b/drivers/staging/mrst/drv/psb_drv.c
@@ -2196,6 +2196,14 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
}
+ if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
+ PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
+ PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
+ PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
+ PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
+ PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
+ PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
+ }
if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
{
@@ -2237,6 +2245,8 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
}
}
}
+ if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
+ PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
} else {
@@ -2248,8 +2258,18 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
}
+ if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
+ dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
+ dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
+ dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
+ dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
+ dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
+ dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
+ }
if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
dev_priv->saveOV_OVADD = arg->overlay.OVADD;
+ if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
+ dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
}
}
@@ -2263,8 +2283,18 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
}
+ if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
+ arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
+ arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
+ arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
+ arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
+ arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
+ arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
+ }
if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
+ if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
+ arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
} else {
if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
@@ -2275,8 +2305,18 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
}
+ if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
+ arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
+ arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
+ arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
+ arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
+ arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
+ arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
+ }
if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
arg->overlay.OVADD = dev_priv->saveOV_OVADD;
+ if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
+ arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
}
}
@@ -2309,6 +2349,58 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
}
}
+ if (arg->subpicture_enable_mask != 0){
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ uint32_t temp;
+ if ( arg->subpicture_enable_mask & REGRWBITS_DSPACNTR){
+ temp = PSB_RVDC32(DSPACNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp &= ~DISPPLANE_BOTTOM;
+ temp |= DISPPLANE_32BPP;
+ PSB_WVDC32(temp, DSPACNTR);
+ }
+ if ( arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR){
+ temp = PSB_RVDC32(DSPBCNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp &= ~DISPPLANE_BOTTOM;
+ temp |= DISPPLANE_32BPP;
+ PSB_WVDC32(temp, DSPBCNTR);
+ }
+ if ( arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR){
+ temp = PSB_RVDC32(DSPCCNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp &= ~DISPPLANE_BOTTOM;
+ temp |= DISPPLANE_32BPP;
+ PSB_WVDC32(temp, DSPCCNTR);
+ }
+ ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ }
+ }
+
+ if (arg->subpicture_disable_mask != 0){
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ uint32_t temp;
+ if ( arg->subpicture_disable_mask & REGRWBITS_DSPACNTR){
+ temp = PSB_RVDC32(DSPACNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp |= DISPPLANE_32BPP_NO_ALPHA;
+ PSB_WVDC32(temp, DSPACNTR);
+ }
+ if ( arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR){
+ temp = PSB_RVDC32(DSPBCNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp |= DISPPLANE_32BPP_NO_ALPHA;
+ PSB_WVDC32(temp, DSPBCNTR);
+ }
+ if ( arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR){
+ temp = PSB_RVDC32(DSPCCNTR);
+ temp &= ~DISPPLANE_PIXFORMAT_MASK;
+ temp |= DISPPLANE_32BPP_NO_ALPHA;
+ PSB_WVDC32(temp, DSPCCNTR);
+ }
+ ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ }
+ }
return 0;
}
diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h
index 5d76960..ded51ba 100644
--- a/drivers/staging/mrst/drv/psb_drv.h
+++ b/drivers/staging/mrst/drv/psb_drv.h
@@ -705,6 +705,13 @@ struct drm_psb_private {
uint32_t saveOV_OGAMC3;
uint32_t saveOV_OGAMC4;
uint32_t saveOV_OGAMC5;
+ uint32_t saveOVC_OVADD;
+ uint32_t saveOVC_OGAMC0;
+ uint32_t saveOVC_OGAMC1;
+ uint32_t saveOVC_OGAMC2;
+ uint32_t saveOVC_OGAMC3;
+ uint32_t saveOVC_OGAMC4;
+ uint32_t saveOVC_OGAMC5;
/*
* extra MDFLD Register state
diff --git a/drivers/staging/mrst/drv/psb_intel_reg.h b/drivers/staging/mrst/drv/psb_intel_reg.h
index c164fff..f8bcb57 100644
--- a/drivers/staging/mrst/drv/psb_intel_reg.h
+++ b/drivers/staging/mrst/drv/psb_intel_reg.h
@@ -568,6 +568,13 @@ struct dpst_guardband {
#define OV_OGAMC2 0x3001C
#define OV_OGAMC1 0x30020
#define OV_OGAMC0 0x30024
+#define OVC_OVADD 0x38000
+#define OVC_OGAMC5 0x38010
+#define OVC_OGAMC4 0x38014
+#define OVC_OGAMC3 0x38018
+#define OVC_OGAMC2 0x3801C
+#define OVC_OGAMC1 0x38020
+#define OVC_OGAMC0 0x38024
/*
* Some BIOS scratch area registers. The 845 (and 830?) store the amount
--
1.7.2.2
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