[Meego-kernel] [PATCH 1/2] Fix GLES App issue

[hitesh.k.patel at intel.com]

From: Hitesh K. Patel <hitesh.k.patel at intel.com>

With previous fix to use PCI API we introduced a bug which will hang the
GLES apps.  This patch will fix the issue.

Change-Id: I63bf1be2c8982f8d56fa30b06cf211742958b0d6
Signed-off-by: Yun Tu(Mark Tu) <yun.tu at intel.com>
Signed-off-by: Hitesh K. Patel <hitesh.k.patel at intel.com>
---
 drivers/staging/mrst/drv/psb_drv.h |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h
index ded51ba..c629a15 100644
--- a/drivers/staging/mrst/drv/psb_drv.h
+++ b/drivers/staging/mrst/drv/psb_drv.h
@@ -1251,30 +1251,38 @@ extern int drm_topaz_sbuswa;
 
 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 {
-	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
+	int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 	uint32_t ret_val = 0;
-	pci_read_config_dword (pci_root, offset, &ret_val);
+	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
+	pci_write_config_dword (pci_root, 0xD0, mcr);
+	pci_read_config_dword (pci_root, 0xD4, &ret_val);
 	pci_dev_put(pci_root);
 	return ret_val;
 }
 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 {
+	int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
-	pci_write_config_dword (pci_root, offset, value);
+	pci_write_config_dword (pci_root, 0xD4, value);
+	pci_write_config_dword (pci_root, 0xD0, mcr);
 	pci_dev_put(pci_root);
 }
 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 {
-	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
+	int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 	uint32_t ret_val = 0;
-	pci_read_config_dword (pci_root, offset, &ret_val);
+	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
+	pci_write_config_dword (pci_root, 0xD0, mcr);
+	pci_read_config_dword (pci_root, 0xD4, &ret_val);
 	pci_dev_put(pci_root);
 	return ret_val;
 }
 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 {
+	int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
-	pci_write_config_dword (pci_root, offset, value);
+	pci_write_config_dword (pci_root, 0xD4, value);
+	pci_write_config_dword (pci_root, 0xD0, mcr);
 	pci_dev_put(pci_root);
 }
 
-- 
1.7.2.2